Henry Cook
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1b3307df32
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Removed has_data fields from all coherence messages, increased message type names to compensate
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2012-03-02 23:51:53 -08:00 |
|
Yunsup Lee
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1054cec087
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add vec countq interface
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2012-03-02 00:43:32 -08:00 |
|
Yunsup Lee
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a8ef5e9e27
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change NMSHR when HAVE_VEC is true
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2012-03-01 01:07:47 -08:00 |
|
Yunsup Lee
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6847160343
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refactor arbiter priorities
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2012-03-01 00:22:34 -08:00 |
|
Andrew Waterman
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012da6002e
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replace tile memory interface with ioTileLink
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
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2012-02-29 03:10:47 -08:00 |
|
Andrew Waterman
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2b1c07c723
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replace ioDCache with ioMem
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2012-02-27 18:36:09 -08:00 |
|
Andrew Waterman
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1d41a41afa
|
remove extraneous constants
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2012-02-27 17:49:48 -08:00 |
|
Andrew Waterman
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e12b9eae93
|
remove ext_mem interface
hindsight is 20/20
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2012-02-26 18:53:39 -08:00 |
|
Yunsup Lee
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f3bb02b2ea
|
refactored dmem arbiter
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2012-02-26 17:38:08 -08:00 |
|
Daiwei Li
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569698b824
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dtlb now arbitrates between cpu, vec, and vec pf
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2012-02-25 22:05:30 -08:00 |
|
Yunsup Lee
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94ba32bbd3
|
change package name and sbt project name to rocket
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2012-02-25 17:09:26 -08:00 |
|
Yunsup Lee
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946e0c6e4e
|
add vector exception infrastructure
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2012-02-25 16:37:56 -08:00 |
|
Andrew Waterman
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4121fb178c
|
clean up mul/div interface; use VU mul if HAVE_VEC
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2012-02-24 19:22:35 -08:00 |
|
Henry Cook
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62837537f4
|
Improved TileIO organization, beginnings of hub implementation
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2012-02-22 18:24:52 -08:00 |
|
Henry Cook
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24a32c2811
|
Refining tilelink interface
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2012-02-22 12:15:47 -08:00 |
|
Henry Cook
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18bd0c232b
|
Added coherence message type enums
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2012-02-22 12:15:47 -08:00 |
|
Andrew Waterman
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7034c9be65
|
new htif protocol and implementation
You must update your fesvr and isasim!
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2012-02-19 23:15:45 -08:00 |
|
Henry Cook
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619929eba1
|
Added coherence tile function defs, with traits and constants
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2012-02-16 00:16:45 -08:00 |
|
Andrew Waterman
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fc5ba769da
|
disable vector unit by default
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2012-02-15 18:58:41 -08:00 |
|
Andrew Waterman
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c13524ad3a
|
fix vcmdq full replay logic
|
2012-02-15 17:49:12 -08:00 |
|
Yunsup Lee
|
6bdf9dc513
|
hwacha integration: now it compiles correctly!
|
2012-02-14 23:34:57 -08:00 |
|
Andrew Waterman
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c78c738f60
|
minor cleanups
|
2012-02-13 03:13:49 -08:00 |
|
Yunsup Lee
|
f47d888feb
|
vvcfgivl and vsetvl works
|
2012-02-09 02:35:21 -08:00 |
|
Andrew Waterman
|
128ec567ed
|
make BTB fully associative; don't use it for JALR
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux. the benfit
was close to nil, anyway.
|
2012-02-09 01:34:00 -08:00 |
|
Yunsup Lee
|
fcc8081c4d
|
hook up the vector command queue
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2012-02-09 01:28:16 -08:00 |
|
Andrew Waterman
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8b6b0f5367
|
add external memory request interface for vec unit
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2012-02-08 22:30:45 -08:00 |
|
Yunsup Lee
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9285a52f25
|
initial vu integration
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2012-02-08 21:43:45 -08:00 |
|
Andrew Waterman
|
e9da2cf66a
|
improve id/ex datapath
move operand selection into decode stage; simplify bypassing
|
2012-02-08 06:47:26 -08:00 |
|
Andrew Waterman
|
5403d069e9
|
add fp loads/stores
|
2012-02-07 23:54:25 -08:00 |
|
Andrew Waterman
|
01a156eb98
|
make # of dcache lines configurable
|
2012-02-01 21:11:45 -08:00 |
|
Andrew Waterman
|
a5a020f97b
|
update chisel and remove SRAM_READ_LATENCY
|
2012-01-23 20:59:38 -08:00 |
|
Henry Cook
|
8623d58724
|
split into two caches, compiles
|
2012-01-18 17:09:35 -08:00 |
|
Andrew Waterman
|
0369b05deb
|
move replays to writeback stage
|
2012-01-17 21:12:31 -08:00 |
|
Andrew Waterman
|
eb657dd250
|
reduce superfluous replays
we only replay after a cache miss if we mis-scheduled the use of a load.
|
2012-01-01 21:28:38 -08:00 |
|
Andrew Waterman
|
b5a8b6dc73
|
fix divider for RV32
|
2011-12-19 16:57:53 -08:00 |
|
Andrew Waterman
|
82700cad72
|
fix multiplier for rv32
|
2011-12-17 07:20:00 -08:00 |
|
Andrew Waterman
|
a8d0cd95e6
|
hellacache now works
|
2011-12-17 03:26:11 -08:00 |
|
Andrew Waterman
|
56c4f44c2a
|
hellacache returns!
but AMOs are unimplemented.
|
2011-12-12 06:49:39 -08:00 |
|
Andrew Waterman
|
ce201559f3
|
Support cache->cpu nacks one cycle after request
|
2011-12-10 00:42:09 -08:00 |
|
Andrew Waterman
|
c01e1f1cef
|
Don't replay from EX stage.
EX replays are now handled from MEM. We may move them to WB.
|
2011-12-09 19:42:58 -08:00 |
|
Andrew Waterman
|
218f63e66e
|
code cleanup/parameterization
|
2011-12-09 00:42:43 -08:00 |
|
Rimas Avizienis
|
fa784d1d7d
|
made setReadLatency argument a parameter defined in consts.scala
|
2011-12-05 00:33:17 -08:00 |
|
Rimas Avizienis
|
bc44572d99
|
bugfixes due to new hcl jar file
|
2011-11-30 21:54:55 -08:00 |
|
Rimas Avizienis
|
80b4253318
|
fixed dcache amo bug, cleaned up testharness, added RDTIME instruction
|
2011-11-16 02:04:28 -08:00 |
|
Rimas Avizienis
|
db87924fbf
|
made eret instruction take an illegal inst exception when ET is set
|
2011-11-14 14:35:10 -08:00 |
|
Rimas Avizienis
|
cd6e463320
|
added ei and di instructions
|
2011-11-14 13:48:49 -08:00 |
|
Rimas Avizienis
|
b791010bb1
|
flush.i invalidates I$ & ITLB, writing PTBR invalidates both TLBs
|
2011-11-14 04:13:13 -08:00 |
|
Rimas Avizienis
|
5b29765917
|
synced up with supervisor mode state in latest ISA simulator
|
2011-11-14 01:37:20 -08:00 |
|
Rimas Avizienis
|
67c7e7e28f
|
cache/tlb bugfixes, increased memory size to 256meg
|
2011-11-13 13:06:35 -08:00 |
|
Rimas Avizienis
|
fbd44ea936
|
added checks for addresses > physical memory size, increased memsize to 64M
|
2011-11-12 23:39:43 -08:00 |
|