riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

refactored dmem arbiter

Browse Source
This commit is contained in:
Yunsup Lee 2012-02-26 17:37:56 -08:00
parent 93f41d3359
commit f3bb02b2ea
3 changed files with 73 additions and 56 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
rocket/src/main/scala/consts.scala
View File

@ -164,9 +164,10 @@ object Constants
val PERM_BITS = 6;
// rocketNBDCache parameters
val DCACHE_PORTS = 2
val CPU_DATA_BITS = 64;
val CPU_TAG_BITS = 9;
val DCACHE_TAG_BITS = 1 + CPU_TAG_BITS;
val DCACHE_TAG_BITS = log2up(DCACHE_PORTS) + CPU_TAG_BITS
val OFFSET_BITS = 6; // log2(cache line size in bytes)
val NMSHR = 2; // number of primary misses
val NRPQ = 16; // number of secondary misses

40
rocket/src/main/scala/cpu.scala
View File

@ -30,7 +30,7 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
val itlb = new rocketITLB(ITLB_ENTRIES);
val vitlb = new rocketITLB(ITLB_ENTRIES);
val ptw = new rocketPTW();
val arb = new rocketDmemArbiter();
val arb = new rocketDmemArbiter(DCACHE_PORTS)
var vu: vu = null
if (HAVE_VEC)
@ -93,8 +93,8 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
dtlb.io.invalidate := dpath.io.ptbr_wen
dtlb.io.status := dpath.io.ctrl.status
arb.io.cpu.req_ppn := dtlb.io.cpu_resp.ppn;
ctrl.io.dmem.req_rdy := dtlb.io.cpu_req.ready && arb.io.cpu.req_rdy;
arb.io.requestor(0).req_ppn := dtlb.io.cpu_resp.ppn;
ctrl.io.dmem.req_rdy := dtlb.io.cpu_req.ready && arb.io.requestor(0).req_rdy;
// connect DTLB to D$ arbiter
ctrl.io.xcpt_ma_ld := io.dmem.xcpt_ma_ld
@ -104,8 +104,8 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
ptw.io.dtlb <> dtlb.io.ptw;
ptw.io.itlb <> itlb.io.ptw;
ptw.io.ptbr := dpath.io.ptbr;
arb.io.ptw <> ptw.io.dmem;
arb.io.mem <> io.dmem
arb.io.requestor(1) <> ptw.io.dmem
arb.io.dmem <> io.dmem
ctrl.io.dpath <> dpath.io.ctrl;
dpath.io.host <> io.host;
@ -129,22 +129,22 @@ class rocketProc(resetSignal: Bool = null) extends Component(resetSignal)
io.imem.itlb_miss := itlb.io.cpu.resp_miss;
// connect arbiter to ctrl+dpath+DTLB
arb.io.cpu.req_val := ctrl.io.dmem.req_val;
arb.io.cpu.req_cmd := ctrl.io.dmem.req_cmd;
arb.io.cpu.req_type := ctrl.io.dmem.req_type;
arb.io.cpu.req_kill := ctrl.io.dmem.req_kill;
arb.io.cpu.req_idx := dpath.io.dmem.req_addr(PGIDX_BITS-1,0);
arb.io.cpu.req_data := dpath.io.dmem.req_data;
arb.io.cpu.req_tag := dpath.io.dmem.req_tag;
ctrl.io.dmem.resp_miss := arb.io.cpu.resp_miss;
ctrl.io.dmem.resp_replay:= arb.io.cpu.resp_replay;
ctrl.io.dmem.resp_nack := arb.io.cpu.resp_nack;
dpath.io.dmem.resp_val := arb.io.cpu.resp_val;
dpath.io.dmem.resp_miss := arb.io.cpu.resp_miss;
dpath.io.dmem.resp_replay := arb.io.cpu.resp_replay;
arb.io.requestor(0).req_val := ctrl.io.dmem.req_val;
arb.io.requestor(0).req_cmd := ctrl.io.dmem.req_cmd;
arb.io.requestor(0).req_type := ctrl.io.dmem.req_type;
arb.io.requestor(0).req_kill := ctrl.io.dmem.req_kill;
arb.io.requestor(0).req_idx := dpath.io.dmem.req_addr(PGIDX_BITS-1,0);
arb.io.requestor(0).req_data := dpath.io.dmem.req_data;
arb.io.requestor(0).req_tag := dpath.io.dmem.req_tag;
ctrl.io.dmem.resp_miss := arb.io.requestor(0).resp_miss;
ctrl.io.dmem.resp_replay:= arb.io.requestor(0).resp_replay;
ctrl.io.dmem.resp_nack := arb.io.requestor(0).resp_nack;
dpath.io.dmem.resp_val := arb.io.requestor(0).resp_val;
dpath.io.dmem.resp_miss := arb.io.requestor(0).resp_miss;
dpath.io.dmem.resp_replay := arb.io.requestor(0).resp_replay;
dpath.io.dmem.resp_type := io.dmem.resp_type;
dpath.io.dmem.resp_tag := arb.io.cpu.resp_tag;
dpath.io.dmem.resp_data := arb.io.cpu.resp_data;
dpath.io.dmem.resp_tag := arb.io.requestor(0).resp_tag;
dpath.io.dmem.resp_data := arb.io.requestor(0).resp_data;
dpath.io.dmem.resp_data_subword := io.dmem.resp_data_subword;
var fpu: rocketFPU = null

86
rocket/src/main/scala/ptw.scala
View File

@ -5,47 +5,63 @@ import Node._;
import Constants._;
import scala.math._;
class ioDmemArbiter extends Bundle
class ioDmemArbiter(n: Int) extends Bundle
{
val ptw = new ioDmem(List("req_val", "req_rdy", "req_cmd", "req_type", "req_idx", "req_ppn", "resp_data", "resp_val", "resp_replay", "resp_nack"));
val cpu = new ioDmem();
val mem = new ioDmem().flip();
val dmem = new ioDmem().flip()
val requestor = Vec(n) { new ioDmem() }
}
class rocketDmemArbiter extends Component
class rocketDmemArbiter(n: Int) extends Component
{
val io = new ioDmemArbiter();
// must delay ppn part of address from PTW by 1 cycle (to match TLB behavior)
val r_ptw_req_val = Reg(io.ptw.req_val);
val r_ptw_req_ppn = Reg(io.ptw.req_ppn);
val r_cpu_req_val = Reg(io.cpu.req_val && io.cpu.req_rdy);
io.mem.req_val := io.ptw.req_val || io.cpu.req_val;
io.mem.req_cmd := Mux(io.ptw.req_val, io.ptw.req_cmd, io.cpu.req_cmd);
io.mem.req_type := Mux(io.ptw.req_val, io.ptw.req_type, io.cpu.req_type);
io.mem.req_idx := Mux(io.ptw.req_val, io.ptw.req_idx, io.cpu.req_idx);
io.mem.req_ppn := Mux(r_ptw_req_val, r_ptw_req_ppn, io.cpu.req_ppn);
io.mem.req_data := io.cpu.req_data;
io.mem.req_tag := Cat(io.cpu.req_tag, io.ptw.req_val);
io.mem.req_kill := io.cpu.req_kill && r_cpu_req_val;
io.ptw.req_rdy := io.mem.req_rdy;
io.cpu.req_rdy := io.mem.req_rdy && !io.ptw.req_val;
io.cpu.resp_miss := io.mem.resp_miss && !io.mem.resp_tag(0).toBool;
val io = new ioDmemArbiter(n)
require(DCACHE_TAG_BITS >= log2up(n) + CPU_TAG_BITS)
io.cpu.resp_nack := io.mem.resp_nack && !r_ptw_req_val
io.ptw.resp_nack := io.mem.resp_nack && r_ptw_req_val
var req_val = Bool(false)
var req_rdy = io.dmem.req_rdy
for (i <- 0 until n)
{
io.requestor(i).req_rdy := req_rdy
req_val = req_val || io.requestor(i).req_val
req_rdy = req_rdy && !io.requestor(i).req_val
}
io.cpu.resp_val := io.mem.resp_val && !io.mem.resp_tag(0).toBool;
io.ptw.resp_val := io.mem.resp_val && io.mem.resp_tag(0).toBool;
var req_cmd = io.requestor(n-1).req_cmd
var req_type = io.requestor(n-1).req_type
var req_idx = io.requestor(n-1).req_idx
var req_ppn = io.requestor(n-1).req_ppn
var req_data = io.requestor(n-1).req_data
var req_tag = io.requestor(n-1).req_tag
var req_kill = io.requestor(n-1).req_kill
for (i <- n-1 to 0 by -1)
{
req_cmd = Mux(io.requestor(i).req_val, io.requestor(i).req_cmd, req_cmd)
req_type = Mux(io.requestor(i).req_val, io.requestor(i).req_type, req_type)
req_idx = Mux(io.requestor(i).req_val, io.requestor(i).req_idx, req_idx)
req_ppn = Mux(Reg(io.requestor(i).req_val), io.requestor(i).req_ppn, req_ppn)
req_data = Mux(Reg(io.requestor(i).req_val), io.requestor(i).req_data, req_data)
req_tag = Mux(io.requestor(i).req_val, Cat(io.requestor(i).req_tag, UFix(i, log2up(n))), req_tag)
req_kill = Mux(Reg(io.requestor(i).req_val), io.requestor(i).req_kill, req_kill)
}
io.cpu.resp_replay := io.mem.resp_replay && !io.mem.resp_tag(0).toBool;
io.ptw.resp_replay := io.mem.resp_replay && io.mem.resp_tag(0).toBool;
io.dmem.req_val := req_val
io.dmem.req_cmd := req_cmd
io.dmem.req_type := req_type
io.dmem.req_idx := req_idx
io.dmem.req_ppn := req_ppn
io.dmem.req_data := req_data
io.dmem.req_tag := req_tag
io.dmem.req_kill := req_kill
io.ptw.resp_data := io.mem.resp_data;
io.cpu.resp_data := io.mem.resp_data;
io.cpu.resp_tag := io.mem.resp_tag >> UFix(1);
for (i <- 0 until n)
{
val tag_hit = io.dmem.resp_tag(log2up(n)-1,0) === UFix(i)
io.requestor(i).resp_miss := io.dmem.resp_miss && tag_hit
io.requestor(i).resp_nack := io.dmem.resp_nack && Reg(io.requestor(i).req_val)
io.requestor(i).resp_val := io.dmem.resp_val && tag_hit
io.requestor(i).resp_replay := io.dmem.resp_replay && tag_hit
io.requestor(i).resp_data := io.dmem.resp_data
io.requestor(i).resp_tag := io.dmem.resp_tag >> UFix(log2up(n))
}
}
class ioPTW extends Bundle
@ -102,9 +118,9 @@ class rocketPTW extends Component
io.dmem.req_cmd := M_XRD;
io.dmem.req_type := MT_D;
// io.dmem.req_addr := req_addr;
io.dmem.req_idx := req_addr(PGIDX_BITS-1,0);
io.dmem.req_ppn := req_addr(PADDR_BITS-1,PGIDX_BITS);
io.dmem.req_ppn := Reg(req_addr(PADDR_BITS-1,PGIDX_BITS))
io.dmem.req_kill := Bool(false)
val resp_val = (state === s_done) || (state === s_l1_fake) || (state === s_l2_fake);
val resp_err = (state === s_error);