change NMSHR when HAVE_VEC is true
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6847160343
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a8ef5e9e27
@ -5,6 +5,10 @@ import scala.math._
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object Constants
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{
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val HAVE_RVC = false
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val HAVE_FPU = true
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val HAVE_VEC = false
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val BR_N = UFix(0, 4);
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val BR_EQ = UFix(1, 4);
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val BR_NE = UFix(2, 4);
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@ -169,7 +173,7 @@ object Constants
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val CPU_TAG_BITS = 9;
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val DCACHE_TAG_BITS = log2up(DCACHE_PORTS) + CPU_TAG_BITS
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val OFFSET_BITS = 6; // log2(cache line size in bytes)
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val NMSHR = 2; // number of primary misses
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val NMSHR = if (HAVE_VEC) 4 else 2 // number of primary misses
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val NRPQ = 16; // number of secondary misses
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val NSDQ = 17; // number of secondary stores/AMOs
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val LG_REFILL_WIDTH = 4; // log2(cache bus width in bytes)
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@ -207,10 +211,6 @@ object Constants
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val ITLB_ENTRIES = 8;
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val START_ADDR = 0x2000;
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val HAVE_RVC = false
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val HAVE_FPU = true
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val HAVE_VEC = false
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val FPU_N = UFix(0, 1);
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val FPU_Y = if (HAVE_FPU) UFix(1, 1) else FPU_N;
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