Andrew Waterman
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e68b039133
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fix misc. D$ control bugs
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2012-11-17 06:47:27 -08:00 |
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Andrew Waterman
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dad7b71062
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provide cmd/addr with cache response
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2012-11-16 21:26:12 -08:00 |
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Andrew Waterman
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cb8ac73045
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provide store data with cache response
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2012-11-16 21:15:13 -08:00 |
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Andrew Waterman
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9e010beffe
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fix D$ refill bug
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2012-11-16 21:05:29 -08:00 |
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Andrew Waterman
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8dce89703a
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new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
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2012-11-16 02:39:33 -08:00 |
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Andrew Waterman
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a90a1790a5
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improve tlb qor
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2012-11-16 01:59:38 -08:00 |
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Andrew Waterman
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ff8c736d94
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move icache invalidate out of request bundle
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2012-11-16 01:55:45 -08:00 |
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Andrew Waterman
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6d10115b19
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fix D$ tag width
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2012-11-15 16:46:39 -08:00 |
|
Yunsup Lee
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be1980dd2d
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refactored vector queue interface
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2012-11-07 01:15:33 -08:00 |
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Yunsup Lee
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8764fe786a
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refactored vector tlb
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2012-11-06 23:53:52 -08:00 |
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Yunsup Lee
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9a02298f6f
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andrew's fix for tlb lockup
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2012-11-06 23:52:58 -08:00 |
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Andrew Waterman
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4d1ca8ba3a
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remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
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2012-11-06 08:13:44 -08:00 |
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Andrew Waterman
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e76892f758
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remove more global constants
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2012-11-06 02:55:45 -08:00 |
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Andrew Waterman
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c5b93798fb
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factor out more global constants
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2012-11-05 23:52:32 -08:00 |
|
Yunsup Lee
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ee081d1671
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modify code to fix UFix := Bits error
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2012-11-05 01:35:55 -08:00 |
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Yunsup Lee
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2a25307a8f
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revamp the vector unit with the new frontend
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2012-11-05 01:35:55 -08:00 |
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Andrew Waterman
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5b20ed71be
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move rd=0 check into bypass logic
before, the check was in the write enable logic, but moving it obviated
an awkward corner case for mtpcr with rd=0.
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2012-11-05 01:30:57 -08:00 |
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Andrew Waterman
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5e103054fd
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fix bug in quine mccluskey
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2012-11-05 00:28:25 -08:00 |
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Andrew Waterman
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e9eca6a95d
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refactor I$ config; remove Top class
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2012-11-04 16:59:36 -08:00 |
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Andrew Waterman
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7380c9fe60
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aggressively clock gate int and fp datapaths
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2012-11-04 16:40:14 -08:00 |
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Andrew Waterman
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bd2d61de03
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use 8T SRAM for I$; gate clock more aggressively
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2012-11-04 16:39:25 -08:00 |
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Andrew Waterman
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fedee6c67d
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add generic error correcting codes
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2012-10-30 01:03:47 -07:00 |
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Andrew Waterman
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5773cbb68a
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rejigger htif to use UncoreConfiguration
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2012-10-18 17:26:03 -07:00 |
|
Henry Cook
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e2eb7ce8e9
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Cleanup git incompetence
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2012-10-16 16:54:58 -07:00 |
|
Henry Cook
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88ac5af181
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Merged consts-as-traits
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2012-10-16 16:32:35 -07:00 |
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Henry Cook
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6cff1c13d8
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Refer to traits moved to uncore, add UncoreConfiguration to top
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2012-10-16 14:22:23 -07:00 |
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Andrew Waterman
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b9a2af697d
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turn off HAVE_VEC as it's currently broken
the new I$/frontend needs to be integrated
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2012-10-16 07:38:19 -07:00 |
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Andrew Waterman
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0a640f2cc6
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make DecodeLogic deterministic (hopefully)
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2012-10-16 04:51:21 -07:00 |
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Andrew Waterman
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5821900329
|
don't refetch from I$ if on same 16B block
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2012-10-16 02:24:38 -07:00 |
|
Andrew Waterman
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b955985b38
|
improve divider QoR
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2012-10-16 02:24:38 -07:00 |
|
Andrew Waterman
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197154c485
|
use BTB for JALR
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2012-10-16 02:24:37 -07:00 |
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Andrew Waterman
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fc648d13a1
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remove old Mux1H; add implicit conversions
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2012-10-16 02:24:37 -07:00 |
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Andrew Waterman
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661f8e635b
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merge I$, ITLB, BTB into Frontend
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2012-10-16 02:24:37 -07:00 |
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Andrew Waterman
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fcd69dba98
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add optional early-out to mul/div
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2012-10-16 02:24:37 -07:00 |
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Andrew Waterman
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27ddff1adb
|
simplify and improve multiplier
|
2012-10-16 02:24:37 -07:00 |
|
Henry Cook
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8970b635b2
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improvements to implicit RocketConfiguration parameter
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2012-10-15 16:29:49 -07:00 |
|
Henry Cook
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a7a4e65690
|
Initial verison of reading config from files
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2012-10-15 16:05:50 -07:00 |
|
Henry Cook
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5d2a470215
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all rocket-specific arbiters in one file and refactored traits slightly
|
2012-10-15 16:05:32 -07:00 |
|
Huy Vo
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1864e41361
|
memserdes + slowio out of rocket and into uncore
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2012-10-10 15:25:24 -07:00 |
|
Huy Vo
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fe21142972
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fixed memdessert unpacking
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2012-10-09 13:03:17 -07:00 |
|
Henry Cook
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9025d0610c
|
first pass at configuration object passed as implicit parameter
|
2012-10-07 22:37:29 -07:00 |
|
Henry Cook
|
dfdfddebe8
|
constants as traits
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2012-10-07 22:20:03 -07:00 |
|
Henry Cook
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b5ff436092
|
decode constant object split into multiple objects
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2012-10-05 15:50:42 -07:00 |
|
Andrew Waterman
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ed8cc4a1cf
|
eliminate D$ probe->WB critical path
|
2012-10-04 09:05:14 -07:00 |
|
Huy Vo
|
e909093f37
|
factoring out uncore into separate uncore repo
|
2012-10-01 16:08:41 -07:00 |
|
Henry Cook
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b9a9664de5
|
uncore and rocket changes for new xact types
|
2012-10-01 10:47:36 -07:00 |
|
Huy Vo
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d9cb96c0ae
|
factored out common stuff to ChiselUtil
|
2012-09-27 22:53:34 -07:00 |
|
Andrew Waterman
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667b4ee858
|
remove Queue flush port (override reset instead)
|
2012-08-22 13:39:19 -07:00 |
|
Andrew Waterman
|
d4a001b867
|
add PriorityMux; use to implement PriorityEncoder
|
2012-08-22 13:38:25 -07:00 |
|
Andrew Waterman
|
743e032f06
|
generalize interface to DecodeLogic
|
2012-08-22 13:38:07 -07:00 |
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