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95f0a688e9
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Merge branch 'release-xacts'
Conflicts:
src/htif.scala
src/icache.scala
src/nbdcache.scala
src/tile.scala
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2013-03-20 17:37:50 -07:00 |
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6d2541aced
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nTiles -> nClients in LogicalNetworkConfig
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2013-03-20 14:12:36 -07:00 |
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5b9f938263
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correctly sign-extend badvaddr, epc, and ebase
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2013-01-24 17:54:59 -08:00 |
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e1225c5114
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standardize IO naming convention
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2013-01-07 13:41:36 -08:00 |
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e9752f1d72
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pipeline host pcr access
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2012-12-06 14:22:07 -08:00 |
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4608660f6e
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torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
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2012-12-04 05:57:53 -08:00 |
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9c857b83f0
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refactor PCR file
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2012-11-27 01:28:06 -08:00 |
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29bc361d6c
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remove global constants; disentangle hwacha a bit
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2012-11-17 17:24:08 -08:00 |
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5a7777fe4d
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clock gate integer datapath more aggressively
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2012-11-17 06:48:44 -08:00 |
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7380c9fe60
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aggressively clock gate int and fp datapaths
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2012-11-04 16:40:14 -08:00 |
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5773cbb68a
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rejigger htif to use UncoreConfiguration
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2012-10-18 17:26:03 -07:00 |
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88ac5af181
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Merged consts-as-traits
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2012-10-16 16:32:35 -07:00 |
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fc648d13a1
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remove old Mux1H; add implicit conversions
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2012-10-16 02:24:37 -07:00 |
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661f8e635b
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merge I$, ITLB, BTB into Frontend
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2012-10-16 02:24:37 -07:00 |
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8970b635b2
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improvements to implicit RocketConfiguration parameter
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2012-10-15 16:29:49 -07:00 |
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9025d0610c
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first pass at configuration object passed as implicit parameter
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2012-10-07 22:37:29 -07:00 |
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dfdfddebe8
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constants as traits
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2012-10-07 22:20:03 -07:00 |
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b94e6915ab
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refactor IPIs; use new tohost/fromhost protocol
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2012-08-03 19:00:34 -07:00 |
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130fa95ed6
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expand HTIF's PCR register space
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2012-07-27 14:52:39 -07:00 |
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4e44ed7400
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allow back pressure on IPI requests
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2012-07-17 22:55:40 -07:00 |
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fd95159837
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INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
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04304fe788
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moving util out into Chisel standard library
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2012-06-06 12:51:26 -07:00 |
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7f6319047e
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update to new scala/chisel/Mem
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2012-06-06 02:47:22 -07:00 |
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7408c9ab69
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removing wires
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2012-05-24 10:42:39 -07:00 |
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a2f6d01c1b
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add programmable coreid register
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2012-05-09 03:09:22 -07:00 |
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e0e1cd5d32
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add IPIs and an IPI test
IPIs are routed through the HTIF, which seems weird, but that makes it
so cores can bring each other out of reset with IPIs.
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2012-05-08 22:58:00 -07:00 |
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86d56ff67b
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refactor cpu/i$/d$ into Tile (rather than Top)
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2012-03-24 16:57:28 -07:00 |
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3a487ac89b
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improve htif<->pcr interface
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2012-03-24 16:57:28 -07:00 |
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54fa6f660d
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new supervisor mode
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2012-03-24 13:03:31 -07:00 |
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8c50c81b81
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drop vec_irq_aux pcr register, now everything goes through badvaddr
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2012-03-17 14:03:57 -07:00 |
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b19d783fbd
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add vector irq handler
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2012-03-14 14:15:28 -07:00 |
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040d62f372
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refactored vector exception handling interface
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2012-03-13 23:45:34 -07:00 |
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b100544b25
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datapath to read out vector state
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2012-03-13 23:45:34 -07:00 |
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a1b30282dd
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major refactoring on vector exception interface
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2012-03-09 01:09:22 -08:00 |
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d4ec7ff4d9
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refined vector exception interface
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2012-03-03 16:11:54 -08:00 |
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1054cec087
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add vec countq interface
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2012-03-02 00:43:32 -08:00 |
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5b0f7ccf68
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updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit
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2012-02-26 17:24:08 -08:00 |
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94ba32bbd3
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change package name and sbt project name to rocket
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2012-02-25 17:09:26 -08:00 |
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946e0c6e4e
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add vector exception infrastructure
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2012-02-25 16:37:56 -08:00 |
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7034c9be65
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new htif protocol and implementation
You must update your fesvr and isasim!
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2012-02-19 23:15:45 -08:00 |
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1b5e39e7fc
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fix bug in BTB
a BTB update followed by a taken branch could cause incorrect control flow.
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2012-02-15 21:36:08 -08:00 |
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725190d0ee
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update to new chisel
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2012-02-11 17:20:33 -08:00 |
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f47d888feb
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vvcfgivl and vsetvl works
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2012-02-09 02:35:21 -08:00 |
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128ec567ed
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make BTB fully associative; don't use it for JALR
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux. the benfit
was close to nil, anyway.
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2012-02-09 01:34:00 -08:00 |
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fcc8081c4d
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hook up the vector command queue
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2012-02-09 01:28:16 -08:00 |
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b3f6f9a5fd
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fix BTB misprediction check for negative addresses
also index BTB with PC, not PC+4
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2012-02-08 15:05:28 -08:00 |
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5403d069e9
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add fp loads/stores
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2012-02-07 23:54:25 -08:00 |
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41855a6d47
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fix missing "otherwise" in PCR file
this fixes timer interrupts for VLSI backend.
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2012-01-26 19:33:55 -08:00 |
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f1c355e3cd
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check pc/effective address sign extension
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2012-01-24 00:15:17 -08:00 |
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a5a020f97b
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update chisel and remove SRAM_READ_LATENCY
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2012-01-23 20:59:38 -08:00 |
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