243 lines
8.6 KiB
Scala
243 lines
8.6 KiB
Scala
package Top
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{
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import Chisel._;
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import Node._;
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import Constants._;
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import scala.math._;
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class ioDpathBTB extends Bundle()
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{
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val current_pc4 = UFix(VADDR_BITS, INPUT);
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val hit = Bool(OUTPUT);
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val target = UFix(VADDR_BITS, OUTPUT);
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val wen = Bool(INPUT);
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val clr = Bool(INPUT);
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val correct_pc4 = UFix(VADDR_BITS, INPUT);
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val correct_target = UFix(VADDR_BITS, INPUT);
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}
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// basic direct-mapped branch target buffer
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class rocketDpathBTB(entries: Int) extends Component
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{
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val io = new ioDpathBTB();
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val addr_bits = ceil(log10(entries)/log10(2)).toInt;
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val idxlsb = 2;
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val idxmsb = idxlsb+addr_bits-1;
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val tagmsb = (VADDR_BITS-idxmsb-1)+(VADDR_BITS-idxlsb)-1;
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val taglsb = (VADDR_BITS-idxlsb);
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val vb_array = Mem(entries, io.wen || io.clr, io.correct_pc4(idxmsb,idxlsb), !io.clr, resetVal = Bool(false));
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val tag_target_array = Mem4(entries, io.wen, io.correct_pc4(idxmsb,idxlsb),
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Cat(io.correct_pc4(VADDR_BITS-1,idxmsb+1), io.correct_target(VADDR_BITS-1,idxlsb)))
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tag_target_array.setReadLatency(0);
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tag_target_array.setTarget('inst);
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val is_val = vb_array(io.current_pc4(idxmsb,idxlsb));
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val tag_target = tag_target_array(io.current_pc4(idxmsb, idxlsb));
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io.hit := is_val && (tag_target(tagmsb,taglsb) === io.current_pc4(VADDR_BITS-1, idxmsb+1));
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io.target := Cat(tag_target(taglsb-1, 0), Bits(0,idxlsb)).toUFix;
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}
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class ioDpathPCR extends Bundle()
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{
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val host = new ioHost(List("from", "from_wen", "to"));
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val debug = new ioDebug(List("error_mode", "log_control"));
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val r = new ioReadPort();
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val w = new ioWritePort();
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val status = Bits(17, OUTPUT);
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val ptbr = UFix(PADDR_BITS, OUTPUT);
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val evec = UFix(VADDR_BITS, OUTPUT);
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val exception = Bool(INPUT);
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val cause = UFix(5, INPUT);
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val badvaddr_wen = Bool(INPUT);
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val pc = UFix(VADDR_BITS+1, INPUT);
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val eret = Bool(INPUT);
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val ei = Bool(INPUT);
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val di = Bool(INPUT);
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val ptbr_wen = Bool(OUTPUT);
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val irq_timer = Bool(OUTPUT);
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val irq_ipi = Bool(OUTPUT);
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val console_data = Bits(8, OUTPUT);
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val console_val = Bool(OUTPUT);
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}
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class rocketDpathPCR extends Component
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{
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val io = new ioDpathPCR();
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val reg_epc = Reg() { UFix() };
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val reg_badvaddr = Reg() { UFix() };
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val reg_ebase = Reg() { UFix() };
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val reg_count = Reg() { UFix() };
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val reg_compare = Reg() { UFix() };
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val reg_cause = Reg() { Bits() };
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val reg_tohost = Reg(resetVal = Bits(0, 64));
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val reg_fromhost = Reg(resetVal = Bits(0, 64));
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val reg_k0 = Reg() { Bits() };
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val reg_k1 = Reg() { Bits() };
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val reg_ptbr = Reg() { UFix() };
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val reg_error_mode = Reg(resetVal = Bool(false));
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val reg_status_vm = Reg(resetVal = Bool(false));
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val reg_status_im = Reg(resetVal = Bits(0,8));
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val reg_status_sx = Reg(resetVal = Bool(true));
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val reg_status_ux = Reg(resetVal = Bool(true));
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val reg_status_ec = Reg(resetVal = Bool(false));
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val reg_status_ef = Reg(resetVal = Bool(false));
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val reg_status_ev = Reg(resetVal = Bool(false));
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val reg_status_s = Reg(resetVal = Bool(true));
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val reg_status_ps = Reg(resetVal = Bool(false));
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val reg_status_et = Reg(resetVal = Bool(false));
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val r_irq_timer = Reg(resetVal = Bool(false));
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val r_irq_ipi = Reg(resetVal = Bool(false));
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val reg_status = Cat(reg_status_sx, reg_status_ux, reg_status_s, reg_status_ps, reg_status_ec, reg_status_ev, reg_status_ef, reg_status_et);
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val rdata = Wire() { Bits() };
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io.ptbr_wen := reg_status_vm.toBool && !io.exception && io.w.en && (io.w.addr === PCR_PTBR);
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io.status := Cat(reg_status_vm, reg_status_im, reg_status);
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io.evec := reg_ebase;
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io.ptbr := reg_ptbr;
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io.host.to := Mux(io.host.from_wen, Bits(0), reg_tohost);
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io.debug.error_mode := reg_error_mode;
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io.r.data := rdata;
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val console_wen = !io.exception && io.w.en && (io.w.addr === PCR_CONSOLE);
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io.console_data := Mux(console_wen, io.w.data(7,0), Bits(0,8));
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io.console_val := console_wen;
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when (io.host.from_wen) {
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reg_tohost <== Bits(0);
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reg_fromhost <== io.host.from;
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}
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otherwise {
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when (!io.exception && io.w.en && (io.w.addr === PCR_TOHOST)) {
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reg_tohost <== io.w.data;
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reg_fromhost <== Bits(0);
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}
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}
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val badvaddr_sign = Mux(io.w.data(VADDR_BITS-1), ~io.w.data(63,VADDR_BITS) === UFix(0), io.w.data(63,VADDR_BITS) != UFix(0))
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when (io.badvaddr_wen) {
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reg_badvaddr <== Cat(badvaddr_sign, io.w.data(VADDR_BITS-1,0)).toUFix;
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}
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when (io.exception && !reg_status_et) {
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reg_error_mode <== Bool(true);
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}
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when (io.exception && reg_status_et) {
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reg_status_s <== Bool(true);
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reg_status_ps <== reg_status_s;
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reg_status_et <== Bool(false);
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reg_epc <== io.pc;
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reg_cause <== io.cause;
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}
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when (!io.exception && io.di) {
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reg_status_et <== Bool(false);
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}
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when (!io.exception && io.ei) {
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reg_status_et <== Bool(true);
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}
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when (!io.exception && io.eret) {
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reg_status_s <== reg_status_ps;
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reg_status_et <== Bool(true);
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}
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when (!io.exception && !io.eret && io.w.en) {
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when (io.w.addr === PCR_STATUS) {
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reg_status_vm <== io.w.data(SR_VM).toBool;
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reg_status_im <== io.w.data(15,8);
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reg_status_sx <== io.w.data(SR_SX).toBool;
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reg_status_ux <== io.w.data(SR_UX).toBool;
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reg_status_s <== io.w.data(SR_S).toBool;
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reg_status_ps <== io.w.data(SR_PS).toBool;
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reg_status_ev <== HAVE_VEC && io.w.data(SR_EV).toBool;
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reg_status_ef <== HAVE_FPU && io.w.data(SR_EF).toBool;
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reg_status_ec <== HAVE_RVC && io.w.data(SR_EC).toBool;
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reg_status_et <== io.w.data(SR_ET).toBool;
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}
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when (io.w.addr === PCR_EPC) { reg_epc <== io.w.data(VADDR_BITS,0).toUFix; }
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when (io.w.addr === PCR_BADVADDR) { reg_badvaddr <== io.w.data(VADDR_BITS,0).toUFix; }
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when (io.w.addr === PCR_EVEC) { reg_ebase <== io.w.data(VADDR_BITS-1,0).toUFix; }
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when (io.w.addr === PCR_COUNT) { reg_count <== io.w.data(31,0).toUFix; }
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when (io.w.addr === PCR_COMPARE) { reg_compare <== io.w.data(31,0).toUFix; r_irq_timer <== Bool(false); }
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when (io.w.addr === PCR_CAUSE) { reg_cause <== io.w.data(4,0); }
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when (io.w.addr === PCR_FROMHOST) { reg_fromhost <== io.w.data; }
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when (io.w.addr === PCR_SEND_IPI) { r_irq_ipi <== Bool(true); }
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when (io.w.addr === PCR_CLR_IPI) { r_irq_ipi <== Bool(false); }
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when (io.w.addr === PCR_K0) { reg_k0 <== io.w.data; }
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when (io.w.addr === PCR_K1) { reg_k1 <== io.w.data; }
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when (io.w.addr === PCR_PTBR) { reg_ptbr <== Cat(io.w.data(PADDR_BITS-1, PGIDX_BITS), Bits(0, PGIDX_BITS)).toUFix; }
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}
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otherwise {
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reg_count <== reg_count + UFix(1);
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}
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when (reg_count === reg_compare) {
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r_irq_timer <== Bool(true);
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}
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io.irq_timer := r_irq_timer;
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io.irq_ipi := r_irq_ipi;
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when (!io.r.en) { rdata <== Bits(0,64); }
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switch (io.r.addr) {
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is (PCR_STATUS) { rdata <== Cat(Bits(0,47), reg_status_vm, reg_status_im, reg_status); }
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is (PCR_EPC) { rdata <== Cat(Fill(64-VADDR_BITS-1, reg_epc(VADDR_BITS)), reg_epc); }
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is (PCR_BADVADDR) { rdata <== Cat(Fill(64-VADDR_BITS-1, reg_badvaddr(VADDR_BITS)), reg_badvaddr); }
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is (PCR_EVEC) { rdata <== Cat(Fill(64-VADDR_BITS, reg_ebase(VADDR_BITS-1)), reg_ebase); }
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is (PCR_COUNT) { rdata <== Cat(Fill(32, reg_count(31)), reg_count); }
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is (PCR_COMPARE) { rdata <== Cat(Fill(32, reg_compare(31)), reg_compare); }
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is (PCR_CAUSE) { rdata <== Cat(Bits(0,59), reg_cause); }
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is (PCR_COREID) { rdata <== Bits(COREID,64); }
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is (PCR_FROMHOST) { rdata <== reg_fromhost; }
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is (PCR_TOHOST) { rdata <== reg_tohost; }
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is (PCR_K0) { rdata <== reg_k0; }
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is (PCR_K1) { rdata <== reg_k1; }
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is (PCR_PTBR) { rdata <== Cat(Bits(0,64-PADDR_BITS), reg_ptbr); }
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otherwise { rdata <== Bits(0,64); }
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}
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}
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class ioReadPort extends Bundle()
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{
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val addr = UFix(5, INPUT);
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val en = Bool(INPUT);
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val data = Bits(64, OUTPUT);
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}
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class ioWritePort extends Bundle()
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{
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val addr = UFix(5, INPUT);
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val en = Bool(INPUT);
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val data = Bits(64, INPUT);
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}
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class ioRegfile extends Bundle()
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{
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val r0 = new ioReadPort();
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val r1 = new ioReadPort();
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val w0 = new ioWritePort();
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}
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class rocketDpathRegfile extends Component
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{
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override val io = new ioRegfile();
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val regfile = Mem4(32, io.w0.data);
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regfile.setReadLatency(0);
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regfile.setTarget('inst);
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regfile.write(io.w0.addr, io.w0.data, io.w0.en);
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io.r0.data := Mux((io.r0.addr === UFix(0, 5)) || !io.r0.en, Bits(0, 64), regfile(io.r0.addr));
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io.r1.data := Mux((io.r1.addr === UFix(0, 5)) || !io.r1.en, Bits(0, 64), regfile(io.r1.addr));
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}
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}
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