Yunsup Lee
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7e6d990bad
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2012-02-29 17:12:02 -08:00 |
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Yunsup Lee
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4939b72ba5
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Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2012-02-29 17:12:02 -08:00 |
|
Yunsup Lee
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20d0088f66
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temporary fix to match bit widths for Mem
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2012-02-29 17:09:31 -08:00 |
|
Henry Cook
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008ad1f45b
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Added 'locking' arbiter that won't rearbitrate until the lock signal on the current winning input is low
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2012-02-29 17:05:06 -08:00 |
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Henry Cook
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c723ef4c50
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ioDecoupled now allows inner bundle to be used in covariant positions, i.e. it accepts subtypes
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2012-02-29 16:46:16 -08:00 |
|
Andrew Waterman
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c38065d0e8
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clean up priority encoders
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2012-02-29 16:13:14 -08:00 |
|
Andrew Waterman
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b9ec69f8f5
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add new Queue singleton
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2012-02-29 14:21:42 -08:00 |
|
Andrew Waterman
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8b519e7ea8
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replace tile memory interface with ioTileLink
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
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2012-02-29 03:10:47 -08:00 |
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Andrew Waterman
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012da6002e
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replace tile memory interface with ioTileLink
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
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2012-02-29 03:10:47 -08:00 |
|
Henry Cook
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ef94f13087
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Broadcast hub nears completion. Still does not handle generation/arbitration for decoupled mem reqs.
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2012-02-29 02:59:27 -08:00 |
|
Henry Cook
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082b38d315
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Broadcast hub nears completion. Still does not handle generation/arbitration for decoupled mem reqs.
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2012-02-29 02:59:27 -08:00 |
|
Henry Cook
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6304aa992f
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Fixed race between read resps/reps and write req/reps in null hub
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2012-02-29 00:44:03 -08:00 |
|
Henry Cook
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8ff6e21e3a
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Fixed race between read resps/reps and write req/reps in null hub
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2012-02-29 00:44:03 -08:00 |
|
Andrew Waterman
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eec369a1c7
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separate memory request command and data
also, merge some VLSI/C++ test harness functionality
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2012-02-28 19:06:23 -08:00 |
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Andrew Waterman
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c99f6bbeb7
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separate memory request command and data
also, merge some VLSI/C++ test harness functionality
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2012-02-28 19:06:23 -08:00 |
|
Henry Cook
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e15284d22c
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Added temporary ioMemHub and made coherence hub implementations depend on it rather than ioMem
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2012-02-28 17:33:32 -08:00 |
|
Henry Cook
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040aa9fe02
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Added temporary ioMemHub and made coherence hub implementations depend on it rather than ioMem
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2012-02-28 17:33:32 -08:00 |
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Daiwei Li
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3f998b1353
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send vcfg and setvl to vu prefetch queues
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2012-02-28 14:54:48 -08:00 |
|
Henry Cook
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ffc7652e01
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Null coherence hub. Begin work on internal tracker logic
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2012-02-27 19:10:15 -08:00 |
|
Henry Cook
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5cc10337b4
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Null coherence hub. Begin work on internal tracker logic
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2012-02-27 19:10:15 -08:00 |
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Andrew Waterman
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7d331858e2
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replace ioDCache with ioMem
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2012-02-27 18:36:09 -08:00 |
|
Andrew Waterman
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2b1c07c723
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replace ioDCache with ioMem
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2012-02-27 18:36:09 -08:00 |
|
Andrew Waterman
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1d41a41afa
|
remove extraneous constants
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2012-02-27 17:49:48 -08:00 |
|
Yunsup Lee
|
3d96a2d4f0
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add fpu.dec.wen := false when HAVE_FPU is turned off
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2012-02-27 14:00:58 -08:00 |
|
Henry Cook
|
3393dc2d31
|
Added probe_req ready sigs, GenArray to Vec
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2012-02-27 11:26:18 -08:00 |
|
Henry Cook
|
f0588a0052
|
Added probe_req ready sigs, GenArray to Vec
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2012-02-27 11:26:18 -08:00 |
|
Henry Cook
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70cdf869ac
|
probe req transactors in coherence hub
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2012-02-27 09:24:33 -08:00 |
|
Henry Cook
|
7a8f53a117
|
probe req transactors in coherence hub
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2012-02-27 09:24:33 -08:00 |
|
Henry Cook
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b6e6d603cc
|
xact init transactors in coherence hub
|
2012-02-27 09:24:32 -08:00 |
|
Henry Cook
|
2275239f33
|
xact init transactors in coherence hub
|
2012-02-27 09:24:32 -08:00 |
|
Yunsup Lee
|
bfd0ae125e
|
upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache
|
2012-02-26 23:46:51 -08:00 |
|
Andrew Waterman
|
6e706c7c74
|
fix yet another AMO-related replay bug
|
2012-02-26 20:20:45 -08:00 |
|
Andrew Waterman
|
e12b9eae93
|
remove ext_mem interface
hindsight is 20/20
|
2012-02-26 18:53:39 -08:00 |
|
Andrew Waterman
|
2d04664a98
|
simplify cpu-cache interface
|
2012-02-26 18:26:29 -08:00 |
|
Andrew Waterman
|
ad713a5d83
|
fix icache ram depth; new chisel
|
2012-02-26 17:51:46 -08:00 |
|
Yunsup Lee
|
f3bb02b2ea
|
refactored dmem arbiter
|
2012-02-26 17:38:08 -08:00 |
|
Huy Vo
|
0fd777f480
|
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
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2012-02-26 17:24:23 -08:00 |
|
Huy Vo
|
aa099a53fa
|
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
|
2012-02-26 17:24:23 -08:00 |
|
Huy Vo
|
93f41d3359
|
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
|
2012-02-26 17:24:23 -08:00 |
|
Huy Vo
|
e22106af3f
|
updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit
|
2012-02-26 17:24:08 -08:00 |
|
Huy Vo
|
5b0f7ccf68
|
updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit
|
2012-02-26 17:24:08 -08:00 |
|
Yunsup Lee
|
766a039ffe
|
small changes to the dtlb arbiter
|
2012-02-26 16:19:50 -08:00 |
|
Daiwei Li
|
69260756bd
|
change ppn and vpn in dtlb from ufix to bits
|
2012-02-26 02:54:31 -08:00 |
|
Yunsup Lee
|
49efe4b744
|
now vu steals cycles from the fpu's fma alu
|
2012-02-26 01:55:07 -08:00 |
|
Daiwei Li
|
47dbc2a417
|
head should be working again
|
2012-02-26 00:30:50 -08:00 |
|
Daiwei Li
|
569698b824
|
dtlb now arbitrates between cpu, vec, and vec pf
|
2012-02-25 22:05:30 -08:00 |
|
Yunsup Lee
|
ca2e70454e
|
change package name and sbt project name to rocket
|
2012-02-25 17:09:26 -08:00 |
|
Yunsup Lee
|
94ba32bbd3
|
change package name and sbt project name to rocket
|
2012-02-25 17:09:26 -08:00 |
|
Yunsup Lee
|
946e0c6e4e
|
add vector exception infrastructure
|
2012-02-25 16:37:56 -08:00 |
|
Yunsup Lee
|
3839e3a318
|
massive refactoring of vector constants
|
2012-02-25 15:55:36 -08:00 |
|