replace tile memory interface with ioTileLink
work in progress towards coherent HTIF. for now, requests are incoherently passed through a null coherence hub.
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parent
ef94f13087
commit
8b519e7ea8
@ -10,22 +10,21 @@ class MemData extends Bundle {
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class MemReqCmd() extends Bundle
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{
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val rw = Bool()
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val addr = UFix(PADDR_BITS - OFFSET_BITS)
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val tag = Bits(MEM_TAG_BITS)
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val addr = UFix(width = PADDR_BITS - OFFSET_BITS)
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val tag = Bits(width = MEM_TAG_BITS)
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}
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class MemResp () extends Bundle
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{
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val tag = Bits(MEM_TAG_BITS)
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val tag = Bits(width = MEM_TAG_BITS)
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val data = Bits(width = MEM_DATA_BITS)
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val valid = Bool()
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}
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class ioMemHub() extends Bundle
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class ioMem() extends Bundle
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{
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val req_cmd = (new ioDecoupled) { new MemReqCmd() }.flip
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val req_data = (new ioDecoupled) { new MemData() }.flip
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val resp = new MemResp()
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val resp = (new ioValid) { new MemResp() }
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}
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class HubMemReq extends Bundle {
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@ -49,7 +48,7 @@ class TransactionInit extends Bundle {
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val t_type = Bits(width = TTYPE_BITS)
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val has_data = Bool()
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val address = Bits(width = PADDR_BITS)
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val address = UFix(width = PADDR_BITS)
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}
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class TransactionInitData extends MemData
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@ -348,8 +347,8 @@ abstract class CoherenceHub extends Component with CoherencePolicy
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class CoherenceHubNull extends Component {
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val io = new Bundle {
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val tile = new ioTileLink()
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val mem = new ioMemHub()
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val tile = new ioTileLink().flip
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val mem = new ioMem
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}
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val x_init = io.tile.xact_init
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@ -362,11 +361,11 @@ class CoherenceHubNull extends Component {
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io.mem.req_data <> io.tile.xact_init_data
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val x_rep = io.tile.xact_rep
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x_rep.bits.t_type := Mux(is_write, X_WRITE_UNCACHED, X_READ_EXCLUSIVE)
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x_rep.bits.tile_xact_id := Mux(is_write, x_init.bits.tile_xact_id, io.mem.resp.tag)
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x_rep.bits.t_type := Mux(io.mem.resp.valid, X_READ_EXCLUSIVE, X_WRITE_UNCACHED)
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x_rep.bits.tile_xact_id := Mux(io.mem.resp.valid, io.mem.resp.bits.tag, x_init.bits.tile_xact_id)
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x_rep.bits.global_xact_id := UFix(0) // don't care
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x_rep.bits.data := io.mem.resp.data
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x_rep.valid := io.mem.resp.valid || is_write
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x_rep.bits.data := io.mem.resp.bits.data
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x_rep.valid := io.mem.resp.valid || x_init.valid && is_write
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}
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@ -388,7 +387,7 @@ class CoherenceHubNoDir extends CoherenceHub {
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val io = new Bundle {
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val tiles = Vec(NTILES) { new ioTileLink() }
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val mem = new ioMemHub
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val mem = new ioMem
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}
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val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(_))
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@ -427,12 +426,12 @@ class CoherenceHubNoDir extends CoherenceHub {
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// Reply to initial requestor
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// Forward memory responses from mem to tile
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val idx = io.mem.resp.tag
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val idx = io.mem.resp.bits.tag
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for( j <- 0 until NTILES ) {
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io.tiles(j).xact_rep.bits.t_type := getTransactionReplyType(t_type_arr.read(idx), sh_count_arr.read(idx))
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io.tiles(j).xact_rep.bits.tile_xact_id := tile_xact_id_arr.read(idx)
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io.tiles(j).xact_rep.bits.global_xact_id := idx
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io.tiles(j).xact_rep.bits.data := io.mem.resp.data
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io.tiles(j).xact_rep.bits.data := io.mem.resp.bits.data
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io.tiles(j).xact_rep.valid := (UFix(j) === init_tile_id_arr.read(idx)) && (io.mem.resp.valid || send_x_rep_ack_arr.read(idx))
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}
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// If there were a ready signal due to e.g. intervening network use:
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