probe req transactors in coherence hub
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@ -161,6 +161,7 @@ class XactTracker(id: Int) extends Component {
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val io = new Bundle {
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val mem_req = (new ioDecoupled) { new HubMemReq() }.flip
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val alloc_req = (new ioDecoupled) { new TrackerAllocReq() }
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val probe_req = (new ioDecoupled) { new ProbeRequest() }.flip
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val can_alloc = Bool(INPUT)
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val xact_finish = Bool(INPUT)
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val p_rep_has_data = Bool(INPUT)
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@ -174,6 +175,7 @@ class XactTracker(id: Int) extends Component {
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val tile_xact_id = Bits(TILE_XACT_ID_BITS, OUTPUT)
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val sharer_count = Bits(TILE_ID_BITS, OUTPUT)
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val t_type = Bits(TTYPE_BITS, OUTPUT)
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val push_p_req = Bits(NTILES, OUTPUT)
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val pop_p_rep = Bits(NTILES, OUTPUT)
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val pop_p_rep_data = Bits(NTILES, OUTPUT)
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val pop_x_init = Bool(OUTPUT)
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@ -356,4 +358,17 @@ class CoherenceHubNoDir extends CoherenceHub {
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!foldR(trackerList.map(t => t.io.busy && coherenceConflict(t.io.addr, init_arb.io.out.bits.xact_init.address)))(_||_)
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// Handle probe request generation
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// Must arbitrate for each request port
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for( j <- 0 until NTILES ) {
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val p_req_arb = (new Arbiter(NGLOBAL_XACTS)) { new ProbeRequest() }
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for( i <- 0 until NGLOBAL_XACTS ) {
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val t = trackerList(i).io
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p_req_arb.io.in(i).bits := t.probe_req.bits
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p_req_arb.io.in(i).ready := t.probe_req.ready
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p_req_arb.io.in(i).valid := t.probe_req.valid && t.push_p_req(j)
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}
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p_req_arb.io.out <> io.tiles(j).probe_req
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}
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}
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