riscv/rocket-chip
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temporary fix to match bit widths for Mem

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This commit is contained in:
Yunsup Lee 2012-02-29 17:09:31 -08:00
parent 012da6002e
commit 20d0088f66
1 changed files with 1 additions and 1 deletions
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2
rocket/src/main/scala/fpu.scala
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@ -615,7 +615,7 @@ class rocketFPU(sfma_latency: Int, dfma_latency: Int) extends Component
Mux(wsrc === UFix(2), fastpipe.io.exc_d,
fastpipe.io.exc_s)))
val waddr = winfo(0).toUFix >> UFix(2)
regfile.write(waddr, wdata, wen(0))
regfile.write(waddr(4,0), wdata, wen(0))
when (wb_reg_valid && wb_ctrl.toint || wen(0)) {
fsr_exc := fsr_exc |