Null coherence hub. Begin work on internal tracker logic
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@ -157,46 +157,149 @@ trait FourStateCoherence extends CoherencePolicy {
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}
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}
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class XactTracker(id: Int) extends Component {
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class XactTracker(id: Int) extends Component with CoherencePolicy {
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val io = new Bundle {
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val mem_req = (new ioDecoupled) { new HubMemReq() }.flip
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val alloc_req = (new ioDecoupled) { new TrackerAllocReq() }
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val probe_req = (new ioDecoupled) { new ProbeRequest() }.flip
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val can_alloc = Bool(INPUT)
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val xact_finish = Bool(INPUT)
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val p_rep_has_data = Bool(INPUT)
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val x_init_has_data = Bool(INPUT)
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val p_rep_data_idx = Bits(log2up(NTILES), INPUT)
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val x_init_data_idx = Bits(log2up(NTILES), INPUT)
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val p_rep_cnt_dec = Bits(NTILES, INPUT)
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val p_req_cnt_inc = Bits(NTILES, INPUT)
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val busy = Bool(OUTPUT)
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val addr = Bits(PADDR_BITS, OUTPUT)
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val init_tile_id = Bits(TILE_ID_BITS, OUTPUT)
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val tile_xact_id = Bits(TILE_XACT_ID_BITS, OUTPUT)
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val sharer_count = Bits(TILE_ID_BITS, OUTPUT)
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val t_type = Bits(TTYPE_BITS, OUTPUT)
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val push_p_req = Bits(NTILES, OUTPUT)
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val pop_p_rep = Bits(NTILES, OUTPUT)
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val pop_p_rep_data = Bits(NTILES, OUTPUT)
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val pop_x_init = Bool(OUTPUT)
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val alloc_req = (new ioDecoupled) { new TrackerAllocReq() }
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val can_alloc = Bool(INPUT)
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val xact_finish = Bool(INPUT)
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val p_rep_has_data = Bool(INPUT)
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val p_rep_data_idx = Bits(log2up(NTILES), INPUT)
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val p_rep_cnt_dec = Bits(NTILES, INPUT)
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val p_req_cnt_inc = Bits(NTILES, INPUT)
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val mem_req = (new ioDecoupled) { new HubMemReq() }.flip
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val probe_req = (new ioDecoupled) { new ProbeRequest() }.flip
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val busy = Bool(OUTPUT)
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val addr = Bits(PADDR_BITS, OUTPUT)
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val init_tile_id = Bits(TILE_ID_BITS, OUTPUT)
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val tile_xact_id = Bits(TILE_XACT_ID_BITS, OUTPUT)
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val sharer_count = Bits(TILE_ID_BITS, OUTPUT)
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val t_type = Bits(TTYPE_BITS, OUTPUT)
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val push_p_req = Bits(NTILES, OUTPUT)
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val pop_p_rep = Bits(NTILES, OUTPUT)
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val pop_p_rep_data = Bits(NTILES, OUTPUT)
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val pop_x_init = Bool(OUTPUT)
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val pop_x_init_data = Bool(OUTPUT)
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val send_x_rep_ack = Bool(OUTPUT)
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val send_x_rep_ack = Bool(OUTPUT)
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}
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val valid = Reg(resetVal = Bool(false))
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val addr = Reg{ Bits() }
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val t_type = Reg{ Bits() }
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val init_tile_id = Reg{ Bits() }
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val tile_xact_id = Reg{ Bits() }
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val probe_done = Reg{ Bits() }
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val s_idle :: s_mem_r :: s_mem_w :: mem_wr :: s_probe :: Nil = Enum(5){ UFix() }
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val state = Reg(resetVal = s_idle)
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val addr_ = Reg{ Bits() }
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val t_type_ = Reg{ Bits() }
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val init_tile_id_ = Reg{ Bits() }
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val tile_xact_id_ = Reg{ Bits() }
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val probe_done = Reg{ Bits() }
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val mem_count = Reg(resetVal = UFix(0, width = log2up(REFILL_CYCLES)))
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io.addr := addr_
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io.init_tile_id := init_tile_id_
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io.tile_xact_id := tile_xact_id_
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io.sharer_count := UFix(NTILES) // TODO: Broadcast only
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io.t_type := t_type_
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/*
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class HubMemReq extends Bundle {
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val rw = Bool()
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val addr = UFix(width = PADDR_BITS-OFFSET_BITS)
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val tag = Bits(width = GLOBAL_XACT_ID_BITS)
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// Figure out which data-in port to pull from
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val data_idx = Bits(width = TILE_ID_BITS)
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val is_probe_rep = Bool()
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}
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class TrackerAllocReq extends Bundle {
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val xact_init = new TransactionInit()
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val t_type = Bits(width = TTYPE_BITS)
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val has_data = Bool()
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val tile_xact_id = Bits(width = TILE_XACT_ID_BITS)
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val address = Bits(width = PADDR_BITS)
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val init_tile_id = Bits(width = TILE_ID_BITS)
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val data_valid = Bool()
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*/
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/*
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when( alloc_req.valid && can_alloc ) {
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valid := Bool(true)
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addr := alloc_req.bits.xact_init.address
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t_type := alloc_req.bits.xact_init.t_type
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init_tile_id := alloc_req.bits.init_tile_id
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tile_xact_id := alloc_req.bits.xact_init.tile_xact_id
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[counter] := REFILL_CYCLES-1 if alloc_req.bits.xact_init.has_data else 0
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}
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when ( alloc_req.bits.data_valid ) {
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io.mem_req.valid :=
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io.mem_req.bits.rw :=
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io.mem_req.bits.addr :=
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io.mem_req.bits.tag :=
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io.mem_req.bits.data_idx :=
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io.mem_req.bits.is_probe_rep :=
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:= io.mem.ready
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}
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when( p_rep_has_data ) {
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io.mem_req.valid :=
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io.mem_req.bits.rw :=
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io.mem_req.bits.addr :=
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io.mem_req.bits.tag :=
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io.mem_req.bits.data_idx :=
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io.mem_req.bits.is_probe_rep :=
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:= io.mem.ready
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}
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val mem_req = (new ioDecoupled) { new HubMemReq() }.flip
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val probe_req = (new ioDecoupled) { new ProbeRequest() }.flip
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push_p_req = Bits(0, width = NTILES)
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pop_p_rep = Bits(0, width = NTILES)
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pop_p_rep_data = Bits(0, width = NTILES)
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pop_x_init = Bool(false)
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pop_x_init_data = Bool(false)
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send_x_rep_ack = Bool(false)
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}
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*/
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//TODO: Decrement the probe count when final data piece is written
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// Connent io.mem.ready sig to correct pop* outputs
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// P_rep and x_init must be popped on same cycle of receipt
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}
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abstract class CoherenceHub extends Component
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abstract class CoherenceHub extends Component with CoherencePolicy
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class CoherenceHubNull extends Component {
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val io = new Bundle {
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val tile = new ioTileLink()
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val mem = new ioMem()
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}
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val x_init = io.tile.xact_init
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val is_write = x_init.bits.t_type === X_WRITE_UNCACHED
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x_init.ready := io.mem.req_rdy
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io.mem.req_val := x_init.valid
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io.mem.req_rw := is_write
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io.mem.req_tag := x_init.bits.tile_xact_id
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io.mem.req_addr := x_init.bits.address
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val x_rep = io.tile.xact_rep
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x_rep.bits.t_type := Bits(width = TTYPE_BITS)
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x_rep.bits.has_data := !is_write
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x_rep.bits.tile_xact_id := Mux(is_write, x_init.bits.tile_xact_id, io.mem.resp_tag)
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x_rep.bits.global_xact_id := UFix(0) // don't care
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x_rep.valid := io.mem.resp_val
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//TODO:
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val x_init_data = io.tile.xact_init_data
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val x_rep_data = io.tile.xact_rep_data
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x_init_data.ready := io.mem.req_rdy
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io.mem.req_wdata := x_init_data.bits.data
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x_rep_data.bits.data := io.mem.resp_data
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x_rep_data.valid := io.mem.resp_val
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// Should be:
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//io.mem.req_data <> x_init_data
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//x_rep_data <> io.mem.resp_data
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}
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class CoherenceHubNoDir extends CoherenceHub {
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