Fixed race between read resps/reps and write req/reps in null hub
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parent
c99f6bbeb7
commit
8ff6e21e3a
@ -329,19 +329,19 @@ class CoherenceHubNull extends Component {
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val x_init = io.tile.xact_init
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val is_write = x_init.bits.t_type === X_WRITE_UNCACHED
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x_init.ready := io.mem.req_cmd.ready
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io.mem.req_cmd.valid := x_init.valid
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x_init.ready := io.mem.req_cmd.ready && !(is_write && io.mem.resp.valid) //stall write req/resp to handle previous read resp
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io.mem.req_cmd.valid := x_init.valid && !(is_write && io.mem.resp.valid)
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io.mem.req_cmd.bits.rw := is_write
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io.mem.req_cmd.bits.tag := x_init.bits.tile_xact_id
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io.mem.req_cmd.bits.addr := x_init.bits.address
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io.mem.req_data <> io.tile.xact_init_data
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val x_rep = io.tile.xact_rep
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x_rep.bits.t_type := X_READ_EXCLUSIVE
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x_rep.bits.t_type := Mux(is_write, X_WRITE_UNCACHED, X_READ_EXCLUSIVE)
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x_rep.bits.tile_xact_id := Mux(is_write, x_init.bits.tile_xact_id, io.mem.resp.tag)
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x_rep.bits.global_xact_id := UFix(0) // don't care
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x_rep.bits.data := io.mem.resp.data
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x_rep.valid := io.mem.resp.valid
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x_rep.valid := io.mem.resp.valid || is_write
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}
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