Added 'locking' arbiter that won't rearbitrate until the lock signal on the current winning input is low
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@ -204,6 +204,45 @@ class Arbiter[T <: Data](n: Int)(data: => T) extends Component {
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dout <> io.out.bits
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}
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class ioLockingArbiter[T <: Data](n: Int)(data: => T) extends Bundle {
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val in = Vec(n) { (new ioDecoupled()) { data } }
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val lock = Vec(n) { Bool() }
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val out = (new ioDecoupled()) { data }.flip()
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}
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class LockingArbiter[T <: Data](n: Int)(data: => T) extends Component {
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val io = new ioLockingArbiter(n)(data)
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val locked = Reg(){ Bits(n) }
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var dout = Wire(){ data }
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var vout = Wire(){ Bool() }
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when((locked && io.lock.toBits).orR) {
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dout := io.in(0).bits
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for (i <- 0 until n) {
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io.in(i).ready := io.out.ready && locked(i)
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vout := io.in(i).valid && locked(i)
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dout := Mux(locked(i), io.in(i).bits, dout)
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}
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} .otherwise {
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io.in(0).ready := io.out.ready
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for (i <- 1 until n) {
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io.in(i).ready := !io.in(i-1).valid && io.in(i-1).ready
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locked(i) := !io.in(i-1).valid && io.in(i-1).ready && io.lock(i)
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}
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dout := io.in(n-1).bits
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for (i <- 1 until n)
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dout = Mux(io.in(n-1-i).valid, io.in(n-1-i).bits, dout)
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vout := io.in(0).valid
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for (i <- 1 until n)
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vout = vout || io.in(i).valid
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}
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vout <> io.out.valid
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dout <> io.out.bits
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}
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object PriorityEncoder
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{
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def apply(in: Bits, n: Int = 0): UFix = {
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