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riscv
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rocket-chip
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7e6d990bad5060fbed0dead78e902ba9ce3be04f
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Yunsup Lee
7e6d990bad
Merge branch 'master' of github.com:ucb-bar/riscv-rocket
2012-02-29 17:12:02 -08:00
uncore
replace tile memory interface with ioTileLink
2012-02-29 03:10:47 -08:00
Description
Rocket Chip Generator (
https://github.com/freechipsproject/rocket-chip
)
13
MiB
Languages
Scala
93.1%
C++
2.1%
Python
2%
Makefile
1.2%
Verilog
0.8%
Other
0.7%