Added probe_req ready sigs, GenArray to Vec
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@ -168,7 +168,8 @@ class XactTracker(id: Int) extends Component {
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val x_init_has_data = Bool(INPUT)
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val p_rep_data_idx = Bits(log2up(NTILES), INPUT)
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val x_init_data_idx = Bits(log2up(NTILES), INPUT)
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val rep_cnt_dec = Bits(NTILES, INPUT)
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val p_rep_cnt_dec = Bits(NTILES, INPUT)
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val p_req_cnt_inc = Bits(NTILES, INPUT)
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val busy = Bool(OUTPUT)
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val addr = Bits(PADDR_BITS, OUTPUT)
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val init_tile_id = Bits(TILE_ID_BITS, OUTPUT)
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@ -218,32 +219,35 @@ class CoherenceHubNoDir extends CoherenceHub {
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val mem = new ioDCache().flip
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}
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val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(_))
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val busy_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} }
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val addr_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS)} }
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val init_tile_id_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
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val tile_xact_id_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_XACT_ID_BITS)} }
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val t_type_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TTYPE_BITS)} }
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val sh_count_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
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val send_x_rep_ack_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} }
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val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(_))
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val do_free_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} }
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val p_rep_has_data_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bool()} }
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val p_rep_data_idx_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=log2up(NTILES))} }
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val rep_cnt_dec_arr = GenArray(NGLOBAL_XACTS){ Wire(){Bits(width=NTILES)} }
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val busy_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val addr_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=PADDR_BITS)} }
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val init_tile_id_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
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val tile_xact_id_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_XACT_ID_BITS)} }
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val t_type_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TTYPE_BITS)} }
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val sh_count_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=TILE_ID_BITS)} }
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val send_x_rep_ack_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val do_free_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val p_rep_has_data_arr = Vec(NGLOBAL_XACTS){ Wire(){Bool()} }
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val p_rep_data_idx_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=log2up(NTILES))} }
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val p_rep_cnt_dec_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=NTILES)} }
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val p_req_cnt_inc_arr = Vec(NGLOBAL_XACTS){ Wire(){Bits(width=NTILES)} }
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for( i <- 0 until NGLOBAL_XACTS) {
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busy_arr.write( UFix(i), trackerList(i).io.busy)
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addr_arr.write( UFix(i), trackerList(i).io.addr)
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init_tile_id_arr.write( UFix(i), trackerList(i).io.init_tile_id)
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tile_xact_id_arr.write( UFix(i), trackerList(i).io.tile_xact_id)
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busy_arr.write( UFix(i), trackerList(i).io.busy)
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addr_arr.write( UFix(i), trackerList(i).io.addr)
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init_tile_id_arr.write( UFix(i), trackerList(i).io.init_tile_id)
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tile_xact_id_arr.write( UFix(i), trackerList(i).io.tile_xact_id)
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t_type_arr.write( UFix(i), trackerList(i).io.t_type)
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sh_count_arr.write( UFix(i), trackerList(i).io.sharer_count)
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send_x_rep_ack_arr.write( UFix(i), trackerList(i).io.send_x_rep_ack)
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trackerList(i).io.xact_finish := do_free_arr.read(UFix(i))
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sh_count_arr.write( UFix(i), trackerList(i).io.sharer_count)
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send_x_rep_ack_arr.write(UFix(i), trackerList(i).io.send_x_rep_ack)
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trackerList(i).io.xact_finish := do_free_arr.read(UFix(i))
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trackerList(i).io.p_rep_has_data := p_rep_has_data_arr.read(UFix(i))
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trackerList(i).io.p_rep_data_idx := p_rep_data_idx_arr.read(UFix(i))
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trackerList(i).io.rep_cnt_dec := rep_cnt_dec_arr.read(UFix(i))
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trackerList(i).io.p_rep_cnt_dec := p_rep_cnt_dec_arr.read(UFix(i))
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trackerList(i).io.p_req_cnt_inc := p_req_cnt_inc_arr.read(UFix(i))
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}
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// Free finished transactions
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@ -308,7 +312,7 @@ class CoherenceHubNoDir extends CoherenceHub {
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val p_rep = io.tiles(j).probe_rep
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flags(j) := p_rep.valid && !p_rep.bits.has_data && (p_rep.bits.global_xact_id === UFix(i))
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}
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rep_cnt_dec_arr.write(UFix(i), flags)
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p_rep_cnt_dec_arr.write(UFix(i), flags)
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}
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// Nack conflicting transaction init attempts
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@ -326,7 +330,7 @@ class CoherenceHubNoDir extends CoherenceHub {
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// the same addr will never be issued; is this ok?
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}
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x_abort.bits.tile_xact_id := x_init.bits.tile_xact_id
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val want_to_abort = conflicts.orR || busy_arr.flatten().andR
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val want_to_abort = conflicts.orR || busy_arr.toBits.andR
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x_abort.valid := want_to_abort && x_init.valid
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aborting(j) := want_to_abort && x_abort.ready
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}
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@ -354,21 +358,27 @@ class CoherenceHubNoDir extends CoherenceHub {
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x_init_data.ready := aborting(j) || foldR(trackerList.map(_.io.pop_x_init_data && init_arb.io.out.bits.init_tile_id === UFix(j)))(_||_)
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}
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alloc_arb.io.out.ready := init_arb.io.out.valid && !busy_arr.flatten().andR &&
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alloc_arb.io.out.ready := init_arb.io.out.valid && !busy_arr.toBits.andR &&
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!foldR(trackerList.map(t => t.io.busy && coherenceConflict(t.io.addr, init_arb.io.out.bits.xact_init.address)))(_||_)
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// Handle probe request generation
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// Must arbitrate for each request port
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val p_req_arb_arr = List.fill(NTILES)((new Arbiter(NGLOBAL_XACTS)) { new ProbeRequest() })
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for( j <- 0 until NTILES ) {
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val p_req_arb = (new Arbiter(NGLOBAL_XACTS)) { new ProbeRequest() }
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for( i <- 0 until NGLOBAL_XACTS ) {
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val t = trackerList(i).io
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p_req_arb.io.in(i).bits := t.probe_req.bits
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p_req_arb.io.in(i).ready := t.probe_req.ready
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p_req_arb.io.in(i).valid := t.probe_req.valid && t.push_p_req(j)
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p_req_arb_arr(j).io.in(i).bits := t.probe_req.bits
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p_req_arb_arr(j).io.in(i).valid := t.probe_req.valid && t.push_p_req(j)
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}
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p_req_arb.io.out <> io.tiles(j).probe_req
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p_req_arb_arr(j).io.out <> io.tiles(j).probe_req
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}
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for( i <- 0 until NGLOBAL_XACTS ) {
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val flags = Bits(width = NTILES)
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for( j <- 0 until NTILES ) {
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flags(j) := p_req_arb_arr(j).io.in(i).ready
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}
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p_rep_cnt_dec_arr.write(UFix(i), flags)
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}
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}
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