Howard Mao
47da284e56
TileLinkNarrower should do nothing if interfaces are the same width
2015-10-13 13:28:47 -07:00
Howard Mao
83df05cb6a
add TileLink data narrower
2015-10-13 12:45:39 -07:00
Howard Mao
993ed86198
move ReorderQueue to utils.scala
2015-10-13 09:49:22 -07:00
Andrew Waterman
0fe16ac1c0
Chisel3 compatibility fixes
2015-09-30 14:37:00 -07:00
Howard Mao
1e7f656527
get release block address from inner release
2015-09-28 15:02:51 -07:00
Andrew Waterman
3b1da4c57e
Revert "replace remaining uses of Vec.fill"
...
This reverts commit b6bb4e42127d1ed42b55ec8b859a4e074b347d47.
2015-09-25 17:06:57 -07:00
Andrew Waterman
20b7a82ab6
Use Vec.fill, not Vec.apply, when making Vec literals
2015-09-25 17:06:52 -07:00
Andrew Waterman
2179cb64ae
Let isRead be true for store-conditional
...
This works around a deadlock bug in the L1 D$, and is arguably true.
2015-09-25 15:28:02 -07:00
Howard Mao
308022210a
use updated NASTI channel constructors
2015-09-25 12:07:27 -07:00
Howard Mao
8c4ac0f4f3
make sure CSR/SCR data width matches xLen
2015-09-25 12:07:03 -07:00
Howard Mao
d1f2d40a90
replace remaining uses of Vec.fill
2015-09-24 17:50:09 -07:00
Howard Mao
3ff830e118
ReorderQueue uses Vec of Bools instead of Bits for roq_free
2015-09-24 17:43:53 -07:00
Howard Mao
83740dfaa5
Merge branch 'master' of github.com:ucb-bar/uncore
2015-09-24 17:10:09 -07:00
Howard Mao
3b86790c3f
replace NASTIMasterIO and NASTISlaveIO with NASTIIO
2015-09-24 16:58:20 -07:00
ducky
ee6754daca
Fix clone -> cloneType
2015-09-24 16:18:25 -07:00
Howard Mao
b4d21148ec
get rid of NASTI error assertion
2015-09-22 09:43:42 -07:00
Howard Mao
8b2341b1b1
use reorder queue instead of extra tag bit to determine TL g_type in NASTI -> TL converter
2015-09-18 09:41:37 -07:00
Howard Mao
bd536d8832
make HTIFModuleIO an anonymous bundle
2015-09-14 12:58:44 -07:00
Howard Mao
9d89d2a558
get rid of MemIO -> TileLink converters
2015-09-14 12:58:44 -07:00
Howard Mao
f9965648f2
fix up some things in tilelink.scala
2015-09-14 12:57:54 -07:00
Howard Mao
64717706a9
get rid of non-NASTI RTC module
2015-09-14 12:57:54 -07:00
Howard Mao
6ee6ea4f1e
use Put/Get/PutBlock/GetBlock constructors in broadcast hub
2015-09-14 12:57:54 -07:00
Howard Mao
ae3d96013a
make TL -> NASTI converter ingest ClientUncachedTileLinkIO and move functionality to Unwrapper
2015-09-14 12:57:54 -07:00
Howard Mao
21f96f382c
split off SCR functionality from HTIF
2015-09-14 12:57:54 -07:00
Howard Mao
bdc6972a8d
separate RTC updates from HTIF
2015-09-14 12:56:44 -07:00
Howard Mao
24f3fac90a
fix broadcast hub and TL -> NASTI converter to support subblock operations
2015-09-14 12:56:44 -07:00
Andrew Waterman
24389a5257
Chisel3 compatibility fixes
2015-09-11 15:41:39 -07:00
Andrew Waterman
350d530766
Use Vec.fill, not Vec.apply, for Vec literals
2015-08-27 10:00:43 -07:00
Andrew Waterman
94287fed90
Avoid type-unsafe assignments
2015-08-27 09:57:36 -07:00
Andrew Waterman
05d311c517
Use Vec.apply, not Vec.fill, for type nodes
2015-08-27 09:47:02 -07:00
Henry Cook
005752e2a6
use the parameters used to create the original object
2015-08-10 14:43:17 -07:00
Andrew Waterman
01fc61ba96
Don't construct so many Vecs
2015-08-05 18:43:59 -07:00
Howard Mao
a551a12d70
add missing Wire wrap in BasicCrossbar
2015-08-05 17:05:31 -07:00
Andrew Waterman
eb6583d607
use cloneType in PhysicalNetworkIO
2015-08-05 16:47:49 -07:00
Andrew Waterman
798ddeb5f5
Chisel3 compatibility: use >>Int instead of >>UInt
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The latter doesn't contract widths anymore.
2015-08-04 13:15:17 -07:00
Andrew Waterman
fb718f03c1
bump scala to 2.11.6
2015-08-03 19:50:58 -07:00
Andrew Waterman
77cf26aeba
Chisel3: Flip order of := and <>
2015-08-03 18:53:39 -07:00
Andrew Waterman
121e4fb511
Flip direction of some bulk connects
2015-08-03 18:01:14 -07:00
Andrew Waterman
a21979a2fa
Bits -> UInt
2015-08-03 18:01:06 -07:00
Andrew Waterman
9c7a41e8d3
Chisel3: bulk connect is not commutative
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We haven't decided if this is a FIRRTL limitation that we should relax,
or a backwards incompatibility we're forced to live with. Should make
for lively debate.
2015-08-01 21:09:00 -07:00
Andrew Waterman
6fc807f069
Chisel3: Avoid subword assignment
2015-08-01 21:08:35 -07:00
Andrew Waterman
6d574f8c1b
Fix incompatible assignment
2015-07-31 00:59:34 -07:00
Andrew Waterman
377e17e811
Add Wire() wrap
2015-07-31 00:32:02 -07:00
Andrew Waterman
0686bdbe28
Avoid cross-module references
...
You can't instantiate a Vec in one module and use it in another.
An idiosyncrasy of the Chisel2 implementation let this one slip by.
In this case, it's just a matter of using def instead of val.
2015-07-30 23:49:06 -07:00
Andrew Waterman
8f7b390353
UInt-> Bits; avoid mixed UInt/SInt code
2015-07-30 23:49:06 -07:00
Andrew Waterman
6c391e3b37
Use UInt(0), not UInt(width=0), for constant 0
2015-07-30 23:49:06 -07:00
Jim Lawson
4c0f996808
Fix typo (juntion -> junctions).
2015-07-30 14:50:28 -07:00
Henry Cook
c70b495f6d
moved buses to junctions repo
2015-07-29 18:04:30 -07:00
Henry Cook
8b1ab23347
update README.md
2015-07-29 11:49:21 -07:00
Henry Cook
4daa20b5fe
simplify .sbt files
2015-07-29 11:49:20 -07:00
Andrew Waterman
a69c749249
Fix compilation with scala 2.11.6
...
We forgot to specify return types on overloaded methods, and a previous
version of the scala compiler failed to flag this as an error.
2015-07-28 16:24:45 -07:00
Andrew Waterman
f8ec6d6393
Chisel3 compatibility: use BitPat for don't-cares
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Also, call the UInt factory instead of the Bits one, for good measure.
2015-07-28 02:46:23 -07:00
Andrew Waterman
0e06c941df
Chisel3 compatibility fixes
2015-07-23 14:58:46 -07:00
Andrew Waterman
3c0475e08b
Add Wire() wrap
2015-07-15 20:24:03 -07:00
Andrew Waterman
2d6b3b2331
Don't use clone
2015-07-15 18:06:27 -07:00
Andrew Waterman
276f53b652
Delete BigMem; it's not used anymore
2015-07-15 17:41:47 -07:00
Andrew Waterman
15cec0eab7
Vec(Reg) -> Reg(Vec)
2015-07-15 12:44:54 -07:00
Andrew Waterman
e76a9d3493
Chisel3: Don't mix Mux types
2015-07-11 14:05:39 -07:00
Andrew Waterman
5dc3da008e
Use Chisel3 SeqMem construct
2015-07-11 13:36:26 -07:00
Henry Cook
fb91e3e1ab
minor metadata API update (0.3.3)
2015-07-09 14:36:09 -07:00
Henry Cook
80ad1eac70
Update README.md
2015-07-08 19:05:18 -07:00
Andrew Waterman
55059632c4
Temporarily use HTIF to push RTC value to cores
2015-07-05 16:19:39 -07:00
Henry Cook
d7cb60e8fa
L2 WritebackUnit bug fix
2015-07-02 13:52:40 -07:00
Andrew Waterman
b4e38192a1
Fix (?) L2$ miss bug
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The victim's metadata was incorrectly used for the new line.
2015-06-24 18:01:56 -07:00
Andrew Waterman
ea76800d1a
Fix data array reset bug
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io.resp.valid could have been valid the cycle after reset, causing the
write mask in the acquire tracker to have an erroneous value after reset.
This caused the L1 I$ to be refilled with the wrong data.
This probably only affects programs loaded with +loadmem and so shouldn't
matter for the EOS24 silicon. It should only affect the first L2 xact,
which, in practice, would be an HTIF write to load the program.
2015-06-11 15:28:23 -07:00
Henry Cook
f3a838cedf
nasti converters, hub bugfix
2015-05-21 19:49:17 -07:00
Henry Cook
c202449e34
first version NASTI IOs
2015-05-14 15:29:49 -07:00
Henry Cook
90c9ee7b04
fix unalloc putblocks
2015-05-14 12:37:35 -07:00
Henry Cook
a7fa77c7fc
track operand size for Gets
2015-05-13 23:28:18 -07:00
Henry Cook
172c372d3e
L2 alloc cleanup
2015-05-12 17:14:06 -07:00
Henry Cook
5fdae2cb61
Merge branch 'master' of github.com:ucb-bar/uncore
2015-05-07 16:18:23 -07:00
Henry Cook
fc883b5049
rm index.html
2015-05-07 16:17:40 -07:00
Henry Cook
8362eba00f
Merge branch 'gh-pages'
2015-05-07 16:16:13 -07:00
Henry Cook
aec24cf1a7
readme
2015-05-07 16:16:07 -07:00
Henry Cook
62b6f24798
Delete TileLink0.3.1Specification.pdf
2015-05-07 15:43:06 -07:00
Henry Cook
90ced93eeb
Merge branch 'master' into gh-pages
2015-05-07 12:35:14 -07:00
Henry Cook
4cef8c9cd4
Added MemIOArbiter
2015-05-07 10:55:38 -07:00
Henry Cook
8832b454ce
add plugins to make scala doc site and publish to ghpages
2015-04-29 15:34:56 -07:00
Henry Cook
1e05fc0525
First pages commit
2015-04-29 13:18:26 -07:00
Henry Cook
3673295d03
network shim cleanup
2015-04-27 16:59:30 -07:00
Henry Cook
09e30041ed
Voluntary Writeback tracker rewrite
2015-04-27 12:56:33 -07:00
Henry Cook
11b5222d01
Refactored WritebackUnit
2015-04-21 22:23:04 -07:00
Henry Cook
4c7969b2b3
Metadata docs and api cleanup
2015-04-20 16:32:09 -07:00
Henry Cook
f66a9fd7a6
simplify ClientMetadata.makeRelease
2015-04-20 10:46:02 -07:00
Henry Cook
6d40a61060
TileLink scala doc and parameter renaming
2015-04-19 22:06:44 -07:00
Henry Cook
ba7a8b1752
TileLink refactor; TileLinkPorts now available. L2Banks no longer have unique ids (suitable for hierarhical P&R).
2015-04-17 16:55:20 -07:00
Henry Cook
ce3271aef2
refactor LNClients and LNManagers
2015-04-15 15:48:36 -07:00
Henry Cook
90f800d87d
Grant bugfixes and more comments
2015-04-13 15:57:06 -07:00
Henry Cook
3cf1778c92
moved ecc lib to uncore, l2 checks for partial write masks when ecc is enabled
2015-04-06 12:22:23 -07:00
Henry Cook
9708d25dff
Restructure L2 state machine and utilize HeaderlessTileLinkIO
2015-04-06 12:19:51 -07:00
Henry Cook
ced627f00a
slight mod to pending_puts
...
cleaner state transition logic
2015-04-01 15:24:53 -07:00
Andrew Waterman
c941f0a68e
New virtual memory implementation (Sv39)
2015-03-27 16:21:29 -07:00
Henry Cook
8959b2e81a
TileLinkEnqueuer
2015-03-26 13:29:52 -07:00
Henry Cook
b7af610569
broadcast hub bugfix
2015-03-26 11:29:04 -07:00
Henry Cook
4176edaa34
clean up tracker allocation
2015-03-26 10:17:51 -07:00
Henry Cook
db5511300d
Merge branch 'l2-subblock-merging'
2015-03-18 23:52:06 -07:00
Henry Cook
3cf033180f
pending read fix
2015-03-18 22:41:09 -07:00
Henry Cook
004ad11af6
cleanup pending signals
2015-03-18 22:14:41 -07:00
Henry Cook
002851f836
disentangle is_hit logic
2015-03-18 21:11:40 -07:00
Henry Cook
b92ea60891
you can 'hit' with putblocks even when the tag doesn't match but you still better writeback
2015-03-18 19:32:46 -07:00