Stephen Twigg
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d2a3b1dc20
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Merge branch 'shapeanalysis'
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2014-05-06 16:49:54 -07:00 |
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Henry Cook
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f8b3117ac0
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bump rocket, uncore
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2014-05-06 13:10:12 -07:00 |
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Henry Cook
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7d6a642c0c
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correct use of function value to initialize MetaDataArray
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2014-05-06 13:00:00 -07:00 |
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Henry Cook
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bc3ef1011e
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correct use of function value to initialize MetaDataArray
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2014-05-06 12:59:45 -07:00 |
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Henry Cook
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445d4f2eee
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bump rocket, uncore
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2014-05-01 01:46:55 -07:00 |
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Henry Cook
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7f690dd9c8
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parameterize metadataarray
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2014-05-01 01:45:45 -07:00 |
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Henry Cook
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45172f1f37
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parameterize metadataarray
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2014-05-01 01:44:59 -07:00 |
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Henry Cook
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ce056b4b89
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client/master -> inner/outer
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2014-04-29 16:50:30 -07:00 |
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Henry Cook
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0237229921
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client/master -> inner/outer
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2014-04-29 16:49:18 -07:00 |
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Henry Cook
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224e286dd3
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New uncore config objects. Backends get their own file. Simplify fpga uncore.
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2014-04-26 19:46:11 -07:00 |
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Henry Cook
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52c6de5641
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DRAMSideLLCLike trait. TSHRFile. New L2 config objects.
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2014-04-26 19:11:36 -07:00 |
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Henry Cook
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519b2ea2b6
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New metadata result trait
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2014-04-26 19:08:56 -07:00 |
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Henry Cook
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3d4273954a
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TileLinkIO.GrantAck -> TileLinkIO.Finish
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2014-04-26 15:19:25 -07:00 |
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Henry Cook
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1b156c6db9
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TileLinkIO.GrantAck -> TileLinkIO.Finish
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2014-04-26 15:18:21 -07:00 |
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Henry Cook
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1163131d1e
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TileLinkIO.GrantAck -> TileLinkIO.Finish
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2014-04-26 15:17:05 -07:00 |
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Henry Cook
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3f53d532c2
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uniquify tilelink conf val name for easier subtyping
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2014-04-26 14:58:38 -07:00 |
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Henry Cook
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fbf6e44376
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fix connection error in fpga uncore
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2014-04-24 11:58:59 -07:00 |
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Henry Cook
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1e062d1bcd
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bump rocket, uncore
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2014-04-23 16:27:34 -07:00 |
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Henry Cook
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f8f29c69b8
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MetaData & friends moved to uncore/
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2014-04-23 16:24:20 -07:00 |
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Henry Cook
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fc825c7103
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MetaData & friends moved to uncore/
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2014-04-23 16:23:51 -07:00 |
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Henry Cook
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f4d326b8d7
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Prep in HellaCache for extracting MetaData to uncore
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2014-04-23 15:43:31 -07:00 |
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Henry Cook
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83a3cb4999
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bump rocket, uncore
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2014-04-22 17:32:39 -07:00 |
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Henry Cook
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39681303b8
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beginning of l2 cache
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2014-04-22 16:58:15 -07:00 |
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Henry Cook
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5c62cff2ce
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put replacement policy in uncore and minor nbdcache cleanups
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2014-04-22 16:53:20 -07:00 |
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Yunsup Lee
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2fefbdd453
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fixes to physical design flow
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2014-04-21 21:36:39 -07:00 |
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Henry Cook
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cfd6748318
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patches to make FAME1/dram IOs compile with up-to-date chisel (bumped)
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2014-04-21 17:26:33 -07:00 |
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Henry Cook
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1bf5439f0b
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include new mm test in benchmarks
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2014-04-18 18:05:30 -07:00 |
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Henry Cook
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5613dc7d1b
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replaced Lists with Vecs
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2014-04-18 17:26:56 -07:00 |
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Andrew Waterman
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09e2ec1f9e
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Fix sign of remainder when dividing by zero
h/t chris
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2014-04-18 16:32:57 -07:00 |
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Jim Lawson
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bf2ff7804e
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Add chisel-dependent.sbt for -DchiselVersion="latest.release"
If -DchiselVersion is specified on the command line, add the
appropriate chisel library to libraryDependencies.
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2014-04-17 17:01:40 -07:00 |
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Henry Cook
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1fa505f9ff
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remove superfluous AVec object
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2014-04-16 17:19:32 -07:00 |
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Andrew Waterman
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3520620fbd
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Remove D$ -> BTB path
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2014-04-15 23:05:02 -07:00 |
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Andrew Waterman
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de492b3cf7
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Fix critical path through integer scoreboard
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2014-04-15 21:28:13 -07:00 |
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Yunsup Lee
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e4c97e7a57
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push tools/tests
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2014-04-14 21:18:22 -07:00 |
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Henry Cook
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691aa4107e
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bump rocket
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2014-04-14 17:13:57 -07:00 |
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Henry Cook
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444d0449e3
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io.cnt bug in serializer
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2014-04-14 17:13:13 -07:00 |
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Henry Cook
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2cb4dbae39
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Refactored uncore constants and tilelink data
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2014-04-10 13:19:50 -07:00 |
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Henry Cook
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5a5f69bfca
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finished uncore constant/tilelink data refactor
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2014-04-10 13:13:46 -07:00 |
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Henry Cook
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b1df49ba30
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removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
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2014-04-10 12:35:43 -07:00 |
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Henry Cook
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fbca7c6bb3
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refactor ioMem and associcated constants. merge Aqcuire and AcquireData
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2014-04-10 12:35:43 -07:00 |
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Henry Cook
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1da8ef2ddf
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Added serdes to decouple cache row size from tilelink data size
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2014-04-10 12:34:12 -07:00 |
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Henry Cook
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910b3b203a
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removed AddressSpaceConstants, CacheConstants, and TileLinkSizeConstants
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2014-04-10 12:32:44 -07:00 |
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Henry Cook
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ebdc0a2692
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merge Aqcuire and AcquireData. cache line size coupled to tilelink data size
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2014-04-10 12:09:52 -07:00 |
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Stephen Twigg
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cac04afc25
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Push riscv-tests, riscv-tools. Repository now consistent such that all tests build, pass in spike, in emulator, and in RTL.
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2014-04-08 22:14:16 -07:00 |
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Stephen Twigg
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f643d38672
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Push rocket, riscv-tests, riscv-tools to consistent state (toolchain rebuild required)
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2014-04-08 16:50:52 -07:00 |
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Stephen Twigg
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e90f2484aa
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Sync with riscv-opcodes (csr register mapping)
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2014-04-08 15:48:37 -07:00 |
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Andrew Waterman
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fb8c7d3da5
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Push rocket
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2014-04-07 23:49:06 -07:00 |
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Andrew Waterman
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3ed8adf032
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Add early out for MUL[W] (not MULH[[S]U])
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2014-04-07 23:48:02 -07:00 |
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Andrew Waterman
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927287da34
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Bypass RAS push/pop
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2014-04-07 23:47:53 -07:00 |
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Andrew Waterman
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817517c663
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Better branch prediction
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2014-04-07 16:08:06 -07:00 |
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