Huy Vo
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08ab076217
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forgot to change package + using fromBits in memserdes instead of manual unpacking
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2012-10-10 15:42:39 -07:00 |
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Huy Vo
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9610622ab0
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moving memserdes + slowio into src
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2012-10-10 12:41:11 -07:00 |
|
Huy Vo
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35f213e735
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Merge branch 'master' of ../rocket-clone
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2012-10-10 12:39:48 -07:00 |
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Andrew Waterman
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7fd4eb6afd
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update uncore
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2012-10-09 18:05:32 -07:00 |
|
Andrew Waterman
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3973aef938
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handle structural hazard on LLC tags
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2012-10-09 18:04:55 -07:00 |
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Andrew Waterman
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c3236e6ee6
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add missing symlink and update uncore
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2012-10-09 17:51:33 -07:00 |
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Huy Vo
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24a49350cc
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reference chip design
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2012-10-09 13:05:56 -07:00 |
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Huy Vo
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916c1019af
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fixed memdessert unpacking
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2012-10-09 13:03:17 -07:00 |
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Huy Vo
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93a0182b96
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everything to get emulator working
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2012-10-01 19:30:11 -07:00 |
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Huy Vo
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8560ea6e40
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rename hwacha -> riscv-hwacha, chisel, riscv-asm-tests-bmarks, and uncore tags
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2012-10-01 19:12:18 -07:00 |
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Huy Vo
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cf8f20584e
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factoring out uncore into separate uncore repo
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2012-10-01 16:08:41 -07:00 |
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Huy Vo
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2413763f3d
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henry's uncore and rocket changes for new xact types
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2012-10-01 16:05:37 -07:00 |
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Henry Cook
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da6ec486f1
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uncore and rocket changes for new xact types
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2012-10-01 10:47:36 -07:00 |
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Huy Vo
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fa8075570a
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move srcs into src dir, factoring out uncore consts into consts
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2012-09-27 12:59:45 -07:00 |
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Huy Vo
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084a0d31c3
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initial commit, all the relevant submodules
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2012-09-26 17:46:17 -07:00 |
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Andrew Waterman
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6546dc84e2
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rename queue to Queue
fixes build with case-insensitive file system
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2012-08-08 22:11:59 -07:00 |
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Andrew Waterman
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aa7fd1f40b
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rename queue to Queue
fixes build with case-insensitive file system
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2012-08-08 22:11:59 -07:00 |
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Andrew Waterman
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17dc2075dd
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fix some LLC control bugs
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2012-08-06 17:10:04 -07:00 |
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Andrew Waterman
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115c25c34b
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fix some LLC control bugs
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2012-08-06 17:10:04 -07:00 |
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Andrew Waterman
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875f3622af
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fix deadlock in coherence hub
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2012-08-03 19:00:03 -07:00 |
|
Andrew Waterman
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962423d2d1
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fix deadlock in coherence hub
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2012-08-03 19:00:03 -07:00 |
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Andrew Waterman
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e346f21725
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fix control bug in LLC
structural hazard on tag ram caused deadlock
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2012-08-03 18:59:37 -07:00 |
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Andrew Waterman
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92b7504c9a
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fix control bug in LLC
structural hazard on tag ram caused deadlock
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2012-08-03 18:59:37 -07:00 |
|
Andrew Waterman
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7a75334bb9
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pipeline LLC further
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2012-07-31 17:45:14 -07:00 |
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Andrew Waterman
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7b9cfd0b90
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pipeline LLC further
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2012-07-31 17:45:14 -07:00 |
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Andrew Waterman
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8db233c9b7
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further pipeline the LLC
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2012-07-30 20:12:11 -07:00 |
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Andrew Waterman
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85dc34df80
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further pipeline the LLC
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2012-07-30 20:12:11 -07:00 |
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Yunsup Lee
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4d4e28c138
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remove reset pin on llc
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2012-07-28 21:14:51 -07:00 |
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Yunsup Lee
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914b6b622d
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remove reset pin on llc
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2012-07-28 21:14:51 -07:00 |
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Yunsup Lee
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465f2efca7
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add reset pin to llc
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2012-07-27 18:44:39 -07:00 |
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Yunsup Lee
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0a2d284d24
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add reset pin to llc
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2012-07-27 18:44:39 -07:00 |
|
Andrew Waterman
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1ae3091261
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memory system bug fixes
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2012-07-26 00:05:21 -07:00 |
|
Andrew Waterman
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1405718ca8
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memory system bug fixes
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2012-07-26 00:05:21 -07:00 |
|
Yunsup Lee
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7736405726
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fix bug in coherence hub, respect xact_rep.ready
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2012-07-23 20:56:55 -07:00 |
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Yunsup Lee
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d0e12c13f6
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fix bug in coherence hub, respect xact_rep.ready
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2012-07-23 20:56:55 -07:00 |
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Andrew Waterman
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df8aff0906
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don't dequeue probe queue during reset
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2012-07-22 21:05:52 -07:00 |
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Andrew Waterman
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c6ac836581
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don't dequeue probe queue during reset
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2012-07-22 21:05:52 -07:00 |
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Andrew Waterman
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d01e70c672
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decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
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2012-07-17 22:55:40 -07:00 |
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Andrew Waterman
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0258dfb23f
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decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
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2012-07-17 22:55:40 -07:00 |
|
Huy Vo
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a79747a062
|
INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
|
Huy Vo
|
18bc14058b
|
INPUT/OUTPUT orderring swapped
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2012-07-12 18:16:57 -07:00 |
|
Andrew Waterman
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62a3ea4113
|
fix some LLC bugs
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2012-07-11 17:56:39 -07:00 |
|
Andrew Waterman
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0aa33bf909
|
fix some LLC bugs
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2012-07-11 17:56:39 -07:00 |
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Andrew Waterman
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1ebfeeca8a
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add L2$
It still has performance bugs but no correctness bugs AFAIK.
|
2012-07-10 05:23:29 -07:00 |
|
Andrew Waterman
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66cf690261
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add L2$
It still has performance bugs but no correctness bugs AFAIK.
|
2012-07-10 05:23:29 -07:00 |
|
Huy Vo
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166b857055
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ioDecoupled -> FIFOIO, ioPipe -> PipeIO
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2012-06-06 18:22:56 -07:00 |
|
Huy Vo
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0c6bade592
|
ioDecoupled -> FIFOIO, ioPipe -> PipeIO
|
2012-06-06 18:22:56 -07:00 |
|
Huy Vo
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9b3161920f
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moving util out into Chisel standard library
|
2012-06-06 12:51:26 -07:00 |
|
Huy Vo
|
f2942f79f9
|
moving util out into Chisel standard library
|
2012-06-06 12:51:26 -07:00 |
|
Huy Vo
|
6f2f1ba21c
|
removing wires
|
2012-05-24 10:42:39 -07:00 |
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