 Henry Cook
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806f897fc4
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nTiles -> nClients in LogicalNetworkConfig
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2013-03-25 17:01:46 -07:00 |
|
 Andrew Waterman
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ce4c1aa566
|
remove aborts
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2013-03-25 17:01:46 -07:00 |
|
|
Henry Cook
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cf76665d09
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writebacks on release network pass asm tests and bmarks
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2013-03-25 17:01:46 -07:00 |
|
|
Henry Cook
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a0dc8d52d6
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using new network and l2 controller
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2013-03-25 17:01:46 -07:00 |
|
 Andrew Waterman
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def11e44b8
|
don't pipe stdout to vcd2vpd
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2013-03-25 17:01:13 -07:00 |
|
|
Andrew Waterman
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ef4927c9ad
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use a named pipe for VCD -> VPD conversion
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2013-03-25 16:19:19 -07:00 |
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Henry Cook
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06f5de3b68
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Merge branch 'release-xacts'
Conflicts:
src/package.scala
src/uncore.scala
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2013-03-20 17:38:46 -07:00 |
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Henry Cook
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4d007d5c40
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changed val names in hub to match new tilelink names
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2013-03-20 17:14:07 -07:00 |
|
|
Henry Cook
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c36b1dfa30
|
Cleaned up uncore and coherence interface. Removed defunct broadcast hub. Trait-ified tilelink bundle components. Added generalized mem arbiter.
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2013-03-20 15:52:39 -07:00 |
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|
Henry Cook
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319b4544d7
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nTiles -> nClients in LogicalNetworkConfig
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2013-03-20 14:30:16 -07:00 |
|
|
Henry Cook
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a7ae7e5758
|
Cleaned up self-probes
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2013-03-20 14:28:20 -07:00 |
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Andrew Waterman
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7b019cb0da
|
rmeove aborts
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2013-03-19 15:30:23 -07:00 |
|
 Yunsup Lee
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bc140ce9bc
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add vec_{vvadd,cmplxmult,matmul} bmarks
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2013-03-19 00:43:51 -07:00 |
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|
Yunsup Lee
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9efe71412f
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add DRAMSideLLCNull
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2013-03-19 00:43:34 -07:00 |
|
|
Yunsup Lee
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f120800aa2
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add DRAMSideLLCNull
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2013-03-19 00:41:28 -07:00 |
|
|
Yunsup Lee
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717a78f964
|
fix seqRead inference
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2013-03-19 00:41:09 -07:00 |
|
|
Henry Cook
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9f0ccbeac5
|
writebacks on release network pass asm tests and bmarks
|
2013-02-28 18:13:41 -08:00 |
|
|
Andrew Waterman
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944f56a766
|
remove duplicate definitions
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2013-02-28 14:55:19 -08:00 |
|
|
Andrew Waterman
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c6695bee7c
|
fix emulator HTIF interface bug
|
2013-02-20 16:11:21 -08:00 |
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|
Andrew Waterman
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fc26150933
|
update to new Mem style
|
2013-02-20 16:10:47 -08:00 |
|
 Eric Love
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17b8654042
|
Merge branch 'master' of github.com:ucb-bar/reference-chip
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2013-02-12 12:47:03 -06:00 |
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|
Yunsup Lee
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61b18a6722
|
push rocket,hwacha,uncore
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2013-02-09 01:05:51 -08:00 |
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Henry Cook
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47a632cc59
|
added support for voluntary wbs over the release network
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2013-01-28 16:39:45 -08:00 |
|
|
Henry Cook
|
1134bbf1a4
|
cleanup disconnected io pins (overwritten network headers)
|
2013-01-27 11:59:17 -08:00 |
|
|
Andrew Waterman
|
dbb61306f0
|
randomize coreid mapping
|
2013-01-26 16:13:14 -08:00 |
|
|
Andrew Waterman
|
4077b22929
|
include fesvr as a library; improve harnesses
|
2013-01-24 23:57:23 -08:00 |
|
|
Andrew Waterman
|
1945fa898b
|
make external clock divider programmable
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2013-01-24 23:40:47 -08:00 |
|
|
Yunsup Lee
|
f37b9d9a7d
|
fix dramsim2 memory model to wrap around
- there was a problem when the I$ speculatively fetched an instruction from an illegal address
|
2013-01-23 01:40:15 -08:00 |
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|
Yunsup Lee
|
217898c7d0
|
emulator depends on source files in src directory
|
2013-01-23 01:39:47 -08:00 |
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|
Yunsup Lee
|
516a64f576
|
commit vec=true
|
2013-01-22 20:24:33 -08:00 |
|
|
Henry Cook
|
b5ccdab514
|
changed val names in hub to match new tilelink names
|
2013-01-22 20:09:21 -08:00 |
|
|
Henry Cook
|
bb5c465bb3
|
Switched back to old, better-tested hub on master
|
2013-01-22 19:57:31 -08:00 |
|
|
Henry Cook
|
5b82d72eb7
|
New TileLink bundle names
|
2013-01-21 17:19:07 -08:00 |
|
|
Henry Cook
|
c211d74e95
|
New TileLink names
|
2013-01-21 17:17:26 -08:00 |
|
|
Henry Cook
|
72bba81a76
|
now using single-ported coherence master
|
2013-01-16 23:58:24 -08:00 |
|
|
Henry Cook
|
fb2644760f
|
single-ported coherence master
|
2013-01-16 23:57:35 -08:00 |
|
|
Henry Cook
|
e33648532b
|
Refactored packet headers/payloads
|
2013-01-15 15:57:06 -08:00 |
|
|
Henry Cook
|
f7c0152409
|
Refactored packet headers/payloads
|
2013-01-15 15:52:47 -08:00 |
|
|
Henry Cook
|
a922b60152
|
Merge branch 'master' of github.com:ucb-bar/reference-chip into network-refactor
|
2013-01-07 14:23:49 -08:00 |
|
|
Henry Cook
|
f2cef8d8d2
|
new IO names, set val/rdy low for unused network inputs, add src/dst setting for tiles, incoherent sig out of tilelink, bump chisel/rocket/uncore
|
2013-01-07 14:19:55 -08:00 |
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|
Henry Cook
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f836bd93e1
|
Bugfix in crossbar ready sigs, added adapter for old hub, removed incoherent sig from tilelink
|
2013-01-07 14:01:39 -08:00 |
|
|
Henry Cook
|
418e3fdf50
|
Bugfix in crossbar ready sigs, added adapter for old hub, removed incoherent sig from tilelink
|
2013-01-07 13:57:48 -08:00 |
|
|
Andrew Waterman
|
bbd010750f
|
add missing #include
|
2013-01-06 04:53:40 -08:00 |
|
|
Andrew Waterman
|
fd727bf8aa
|
add some of the zedboard fpga infrastructure
you can elaborate the RTL in fpga/build/vcs-sim-rtl, but there's no harness
for VCS simulation yet.
|
2013-01-06 03:58:10 -08:00 |
|
|
Andrew Waterman
|
03df2c3766
|
update .gitignores
|
2013-01-06 03:58:10 -08:00 |
|
|
Henry Cook
|
d0805359a5
|
Refactored uncore conf
|
2012-12-13 11:46:29 -08:00 |
|
|
Henry Cook
|
400d48e3de
|
Refactored uncore conf
|
2012-12-13 11:39:14 -08:00 |
|
|
Henry Cook
|
1d7f1a8182
|
Removed dummy tile instances
|
2012-12-12 16:44:03 -08:00 |
|
|
Henry Cook
|
0e73cc8c12
|
Removed dummy tile instances
|
2012-12-12 16:41:21 -08:00 |
|
|
Henry Cook
|
177909c955
|
Initial version of phys/log network compiles
|
2012-12-12 11:15:10 -08:00 |
|