uncore and rocket changes for new xact types
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@ -3,14 +3,17 @@ package rocket
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import Chisel._
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import Constants._
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class PhysicalAddress extends Bundle {
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val addr = UFix(width = PADDR_BITS - OFFSET_BITS)
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}
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class MemData extends Bundle {
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val data = Bits(width = MEM_DATA_BITS)
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}
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class MemReqCmd() extends Bundle
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class MemReqCmd() extends PhysicalAddress
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{
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val rw = Bool()
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val addr = UFix(width = PADDR_BITS - OFFSET_BITS)
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val tag = Bits(width = MEM_TAG_BITS)
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}
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@ -165,7 +168,7 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
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io.probe_req.valid := Bool(false)
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io.probe_req.bits.p_type := co.getProbeRequestType(x_type_, UFix(0))
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io.probe_req.bits.global_xact_id := UFix(id)
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io.probe_req.bits.address := addr_
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io.probe_req.bits.addr := addr_
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io.push_p_req := Bits(0, width = ntiles)
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io.pop_p_rep := Bits(0, width = ntiles)
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io.pop_p_rep_data := Bits(0, width = ntiles)
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@ -178,7 +181,7 @@ class XactTracker(ntiles: Int, id: Int, co: CoherencePolicy) extends Component {
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switch (state) {
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is(s_idle) {
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when( io.alloc_req.valid && io.can_alloc ) {
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addr_ := io.alloc_req.bits.xact_init.address
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addr_ := io.alloc_req.bits.xact_init.addr
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x_type_ := io.alloc_req.bits.xact_init.x_type
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init_tile_id_ := io.alloc_req.bits.tile_id
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tile_xact_id_ := io.alloc_req.bits.xact_init.tile_xact_id
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@ -272,7 +275,7 @@ class CoherenceHubNull(co: ThreeStateIncoherence) extends CoherenceHub(1, co)
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io.mem.req_cmd.valid := x_init.valid && !(is_write && io.mem.resp.valid)
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io.mem.req_cmd.bits.rw := is_write
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io.mem.req_cmd.bits.tag := x_init.bits.tile_xact_id
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io.mem.req_cmd.bits.addr := x_init.bits.address
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io.mem.req_cmd.bits.addr := x_init.bits.addr
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io.mem.req_data <> io.tiles(0).xact_init_data
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val x_rep = io.tiles(0).xact_rep
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@ -432,7 +435,7 @@ class CoherenceHubBroadcast(ntiles: Int, co: CoherencePolicy) extends CoherenceH
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val conflicts = Vec(NGLOBAL_XACTS) { Bool() }
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for( i <- 0 until NGLOBAL_XACTS) {
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val t = trackerList(i).io
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conflicts(i) := t.busy && x_init.valid && co.isCoherenceConflict(t.addr, x_init.bits.address)
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conflicts(i) := t.busy && x_init.valid && co.isCoherenceConflict(t.addr, x_init.bits.addr)
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}
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x_abort.bits.tile_xact_id := x_init.bits.tile_xact_id
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want_to_abort_arr(j) := x_init.valid && (conflicts.toBits.orR || busy_arr.toBits.andR || (!x_init_data_dep_list(j).io.enq.ready && co.messageHasData(x_init.bits)))
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