Howard Mao
a809a1712a
make sure clocks and reset signals get intialized properly
2016-06-08 15:38:39 -07:00
Donggyu Kim
99b257316e
replace emulator with verilator for chisel3
2016-06-08 02:43:54 -07:00
Howard Mao
08e53a00f0
bump cde for better match failure stack trace
2016-06-07 16:15:10 -07:00
Howard Mao
2cd897e240
Revert "include the unmatched field in CDEMatchError"
...
This reverts commit ff2937a788
2016-06-07 16:13:01 -07:00
Howard Mao
8db27a36c4
fix Tile reset power on behavior
2016-06-07 11:06:38 -07:00
Palmer Dabbelt
e6c4372332
Fix "make run-asm-tests" for Chisel 3
...
This was just a missing Makefrag-verilog dependency (the .d file).
2016-06-06 21:36:55 -07:00
Andrew Waterman
2c17f828b6
bump chisel and rocket
2016-06-06 21:36:51 -07:00
Wesley W. Terpstra
5495705acf
Configs: enable AHB for FPGAs
2016-06-06 21:36:09 -07:00
Wesley W. Terpstra
ef27cc3a33
RocketChip: handle atomics only if needed
2016-06-06 21:36:03 -07:00
Wesley W. Terpstra
3e0ec855cf
RocketChip: add ahb mem interface
2016-06-06 21:35:59 -07:00
Wesley W. Terpstra
d2b505f2d2
RocketChip: rename mem to mem_axi in preparation for new bus type
2016-06-06 21:35:55 -07:00
Wesley W. Terpstra
2086c0d603
Configs: add a parameter to control the memory subsystem interface
2016-06-06 21:35:43 -07:00
Wesley W. Terpstra
2ddada1732
ahb: add mmio_ahb option
2016-06-06 21:35:39 -07:00
Wesley W. Terpstra
31f1dcaf84
ahb: rename mmio outputs to mmio_axi
2016-06-06 21:35:34 -07:00
Wesley W. Terpstra
7a24527448
ahb: make MMIO channels specifiy bus type (we will have more than one bridge)
2016-06-06 21:35:30 -07:00
Wesley W. Terpstra
f3a557b67b
ahb: AHB parameters should be site specific
...
Conflicts:
src/main/scala/Configs.scala
2016-06-06 21:35:24 -07:00
Howard Mao
172c4f25f4
bump groundtest and uncore
2016-06-06 17:45:30 -07:00
Howard Mao
ff2937a788
include the unmatched field in CDEMatchError
2016-06-06 11:23:20 -07:00
Andrew Waterman
d24c87f8ba
Update PLIC/PRCI address map ( #124 )
2016-06-06 04:51:55 -07:00
Andrew Waterman
ece3ab9c3d
Refactor AddrMap and its usage ( #122 )
2016-06-03 17:29:05 -07:00
Andrew Waterman
c8338ad809
Instantiate Debug Module ( #119 )
2016-06-02 10:53:41 -07:00
Andrew Waterman
1311e78d3f
Add blocking D$ flush support
2016-05-31 19:28:41 -07:00
Howard Mao
50e3caef36
get rid of Zscale file I missed last time
2016-05-31 14:33:38 -07:00
Andrew Waterman
44a216038f
Use more generic TileLinkWidthAdapter
2016-05-27 13:38:13 -07:00
Andrew Waterman
10f0e13c25
Use more parsimonious queue depths
2016-05-26 18:04:22 -07:00
Andrew Waterman
3cc236e9c4
By default, use same TileLink width everywhere
...
When there's no L2 with a wide interface, having wider TileLink
is only disadvantageous.
2016-05-26 18:04:01 -07:00
Wesley W. Terpstra
976d4d3184
ahb: AHB parameters should match TileLink parameters by default
...
Closes #116
2016-05-25 18:01:25 -07:00
Andrew Waterman
ec0d178010
Support M-mode-only implementations
2016-05-25 15:40:53 -07:00
Andrew Waterman
da105a5944
Don't allow travis to recurse through submodules
2016-05-25 13:27:49 -07:00
Wesley W. Terpstra
da566e7d6a
build: use local sbt when building firrtl
2016-05-25 11:48:03 -07:00
Andrew Waterman
e82c080c3c
Add blocking D$
2016-05-25 11:09:50 -07:00
Andrew Waterman
a8462d3cfc
bump chisel
2016-05-25 11:09:50 -07:00
Howard Mao
f52fc655a5
remove zscale
2016-05-19 09:43:15 -07:00
Colin Schmidt
abb0e2921b
return non-zero exit codes when an assertion fires
...
This ensures that assertion failures, which currently print a message to
the console but return a successful exit code, now will cause non-zero
exit code. This is meant to help automated tools like travis and
buildbot do a better job at catching assertions.
This impacts the various run-* targets in the simulation
directories.
2016-05-18 12:57:58 -07:00
Colin Schmidt
b396c68577
bump torture for priv-1.9 test-env
2016-05-17 22:02:38 -07:00
Colin Schmidt
b0ae003981
add firrtl to regression makefile
...
this makes it easier to test chisel3 builds
e.g. the local buildbot can now test a bunch of configs
2016-05-17 17:34:20 -07:00
Andrew Waterman
684d902059
Fix PLIC instantiation when S-mode is disabled
2016-05-13 11:22:46 -07:00
Andrew Waterman
6aa708bcee
Disable MMIO by default to avoid disconnected nets
2016-05-11 13:12:39 -07:00
Christopher Celio
3fe00ce32a
Update README.md
...
- Removed instruction to checkout riscv-tests (as they are now globally installed when building the riscv-tools).
- Clarified the riscv-tools set-up information to clarify that the rocket-chip/riscv-tools is the version to build.
2016-05-10 22:12:02 -07:00
Andrew Waterman
fbff46d27d
bump rocket
2016-05-10 10:57:03 -07:00
Andrew Waterman
aac89ca1f0
Add PLIC
2016-05-10 00:27:31 -07:00
Howard Mao
df479d7935
don't make MIFTagBits a computed parameter
2016-05-08 11:04:58 -07:00
Howard Mao
3b0e9167fa
add AXI to AHB converter and more conformant HASTI RAM
2016-05-06 11:32:03 -07:00
Howard Mao
a875eb9c31
update riscv-tools for bbl fix
2016-05-05 19:36:34 -07:00
Howard Mao
18ffe7b1ec
don't use +verbose in vsim .run rule
2016-05-04 23:01:14 -07:00
Andrew Waterman
8b06947446
Run bmarks faster (hopefully)
2016-05-04 22:47:34 -07:00
Howard Mao
f1baa4aecc
update riscv-tests so that mm benchmark doesn't run forever
2016-05-04 21:28:55 -07:00
Howard Mao
dfcb73b6c9
groundtest only needs to write to a single tohost
2016-05-03 20:21:13 -07:00
Howard Mao
4045a07eda
Remove need for separate riscv-tests for groundtest
2016-05-03 18:29:46 -07:00
Howard Mao
8f891437b5
fix CacheFillTest
2016-05-03 14:57:05 -07:00
