Andrew Waterman
15f4af19cf
Remove HTIF CPU port
2016-05-03 13:55:59 -07:00
Howard Mao
487d0b356e
fixes to get groundtest working with priv-1.9 changes
2016-05-03 13:09:44 -07:00
Andrew Waterman
c7c8ae5468
Instantiate PRCI block
2016-05-02 18:08:33 -07:00
Andrew Waterman
6d1e82bddf
Remove mtohost/mfromhost/mipi CSRs; stub out Rocket CSR port
2016-05-02 15:21:55 -07:00
Andrew Waterman
c4d2d29e80
Stub out debug module, rather than leaving it floating
2016-04-30 22:37:39 -07:00
Andrew Waterman
46bbbba5e6
New address map
2016-04-30 20:59:36 -07:00
Andrew Waterman
d0aa4c722d
More WIP on new memory map
2016-04-28 16:15:31 -07:00
Andrew Waterman
1f211b37df
WIP on new memory map
2016-04-27 14:57:54 -07:00
Colin Schmidt
48170fd9aa
add default cases to configs that use CDEMatchError
...
this avoids filling in the stack trace every time
a config doesn't contain the parameter
2016-04-22 12:14:58 -07:00
Howard Mao
f7af908969
put memory into the address map and no longer use MMIOBase
2016-04-21 18:53:16 -07:00
Howard Mao
325d3671c4
add write data id field for AXI3 compat
2016-04-20 09:21:43 -07:00
Howard Mao
0cf6b1f118
merge ATOS changes from hurricane
2016-04-20 09:21:43 -07:00
Scott Beamer
c19931ba03
add technical report to readme
2016-04-19 16:17:50 -07:00
Yunsup Lee
4afc9c69a0
streamline sbt
2016-04-19 14:22:22 -07:00
Palmer Dabbelt
7c33d88861
Merge pull request #90 from ucb-bar/elaborate-once
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Bump Chisel3, to elaborate circuits once
2016-04-18 21:04:55 -07:00
Palmer Dabbelt
85c86994a0
Bump Chisel3, to elaborate circuits once
2016-04-18 14:54:17 -07:00
Matthew Naylor
cbfd7fd13a
Remove tracegen scripts, now in groundtest
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And bump groundtest.
2016-04-14 14:01:48 -07:00
Howard Mao
c5838dd9b3
Fix narrow read/write behavior for AXI converters and fix L2 bugs
...
Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.
There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.
There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.
2016-04-12 15:39:15 -07:00
Andrew Waterman
c4c6bd1040
Bump rocket.
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Closes #84 .
2016-04-01 18:20:32 -07:00
Andrew Waterman
b43a85e2e8
Make ExampleSmallConfig/DefaultRV32Config smaller
2016-04-01 18:18:08 -07:00
Andrew Waterman
6878e3265f
Default RowBits to TileLink width, not XLen
2016-04-01 18:18:08 -07:00
Andrew Waterman
46d7dceb1e
Disable printf/assert during reset
2016-04-01 18:18:08 -07:00
Andrew Waterman
cd9e07d8e7
Update sbt to 0.13.11
2016-04-01 18:18:08 -07:00
Andrew Waterman
bd3dba7f66
Fix LR/SC livelock bug
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Closes #74 .
2016-04-01 18:18:08 -07:00
Henry Cook
35d02c5096
LRSC fix. RocketChipNetwork moved to uncore.
2016-04-01 18:09:00 -07:00
Howard Mao
5337c7d22d
add more complicated memtests to travis
2016-03-31 18:42:14 -07:00
Howard Mao
4f06a5ff6b
add memtest config for testing memory channel mux
2016-03-31 18:41:56 -07:00
Howard Mao
5a74a9b1e7
switch memory interconnect from AXI to TileLink
2016-03-31 18:18:30 -07:00
Howard Mao
6d5c98da7d
point submodule pointer to proper commit hash
2016-03-31 15:03:33 -07:00
Howard Mao
7c3b57b8fa
switch MMIO network to TileLink
2016-03-31 14:30:10 -07:00
Howard Mao
ab540d536a
bump uncore for split metadata chisel3 fix
2016-03-30 22:11:45 -07:00
Howard Mao
c831a0a4e5
use scala firrtl instead of stanza firrtl
2016-03-30 19:35:25 -07:00
Howard Mao
be612e3843
bump rocket and uncore
2016-03-30 19:23:19 -07:00
Howard Mao
c081a36893
Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter"
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This reverts commit 5378f79b50
2016-03-30 19:06:32 -07:00
Howard Mao
e77900f540
Revert "switch back to Chisel2 for verilog build for now"
...
This reverts commit 3673365b08
2016-03-30 19:00:38 -07:00
Howard Mao
8e601f26e1
switch back to the correct chisel3 and firrtl branches
2016-03-30 18:59:33 -07:00
Howard Mao
1e03408323
get rid of mt benchmark suite
2016-03-29 20:16:07 -07:00
Howard Mao
cf716fea58
fix mm_dramsim2
2016-03-29 20:16:07 -07:00
Howard Mao
3673365b08
switch back to Chisel2 for verilog build for now
2016-03-29 20:16:07 -07:00
Howard Mao
265a82427e
add DefaultL2Config and DualCoreConfig to travis
2016-03-29 20:16:07 -07:00
Howard Mao
ad93e0226d
Changes to prepare for switch to TileLink interconnect
...
We are planning on switching to a TileLink interconnect throughout and
convert to AXI only on the very edge. Therefore, we need to get rid of
all the existing AXI masters other than the TileLink to AXI converter.
* Get rid of DMA engine for now
* Connect RTC to TileLink interconnect instead of AXI interconnect
2016-03-29 20:16:07 -07:00
jackkoenig
5378f79b50
Bump chisel3 and firrtl, add support for firrtl $ delimiter
2016-03-29 20:16:07 -07:00
Howard Mao
38649bd4c1
some edits to groundtest regression tests
2016-03-29 20:16:07 -07:00
Howard Mao
9b9c662952
fix w_last wire
2016-03-29 20:16:07 -07:00
Howard Mao
2b61f28356
don't test DMA controller for now
2016-03-29 20:16:07 -07:00
Howard Mao
e1a03cc9ac
fix issue with partial writemasks
2016-03-29 20:16:07 -07:00
Andrew Waterman
6c48dc3471
Use more sensible knob values for SmallConfig
2016-03-25 14:18:24 -07:00
Andrew Waterman
cce89f5fbc
Bump rocket
2016-03-25 14:18:15 -07:00
Andrew Waterman
d1639416cb
Merge pull request #77 from ucb-bar/chisel3
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Preliminary Chisel 3 Support
2016-03-24 12:56:36 -07:00
Palmer Dabbelt
39cf945efb
Use Chisel 3 to build verilog on Travis
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Chisel 3 can't build the C++ emulator, so we currently can't have direct
support for testing RocketChip. We can at least test to see if the
Verilog builds when run through Chisel 3, which this patch does.
2016-03-24 12:00:13 -07:00
