4608660f6e
torture revealed a couple bugs
...
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
2012-12-04 05:57:53 -08:00
9c857b83f0
refactor PCR file
2012-11-27 01:28:06 -08:00
352bb464b5
clock gate X/M and M/W store data registers
2012-11-26 20:33:41 -08:00
de2f28193a
get rid of more global constants
2012-11-25 04:24:25 -08:00
c036cdc1ea
add option for 2-cycle load-use delay
2012-11-24 22:01:08 -08:00
72f94d1141
fix virtual address sign extension detection
2012-11-20 04:06:57 -08:00
29bc361d6c
remove global constants; disentangle hwacha a bit
2012-11-17 17:24:08 -08:00
5a7777fe4d
clock gate integer datapath more aggressively
2012-11-17 06:48:44 -08:00
8dce89703a
new D$ with better QoR and AMO pipelining
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Vector unit is disabled because nack handling needs to be fixed.
2012-11-16 02:39:33 -08:00
8764fe786a
refactored vector tlb
2012-11-06 23:53:52 -08:00
4d1ca8ba3a
remove more global consts; refactor DTLBs
...
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
2012-11-06 08:13:44 -08:00
c5b93798fb
factor out more global constants
2012-11-05 23:52:32 -08:00
5b20ed71be
move rd=0 check into bypass logic
...
before, the check was in the write enable logic, but moving it obviated
an awkward corner case for mtpcr with rd=0.
2012-11-05 01:30:57 -08:00
7380c9fe60
aggressively clock gate int and fp datapaths
2012-11-04 16:40:14 -08:00
5773cbb68a
rejigger htif to use UncoreConfiguration
2012-10-18 17:26:03 -07:00
88ac5af181
Merged consts-as-traits
2012-10-16 16:32:35 -07:00
197154c485
use BTB for JALR
2012-10-16 02:24:37 -07:00
661f8e635b
merge I$, ITLB, BTB into Frontend
2012-10-16 02:24:37 -07:00
27ddff1adb
simplify and improve multiplier
2012-10-16 02:24:37 -07:00
8970b635b2
improvements to implicit RocketConfiguration parameter
2012-10-15 16:29:49 -07:00
9025d0610c
first pass at configuration object passed as implicit parameter
2012-10-07 22:37:29 -07:00
dfdfddebe8
constants as traits
2012-10-07 22:20:03 -07:00
0a97d6ab4d
type casting
2012-07-18 13:03:35 -07:00
4e44ed7400
allow back pressure on IPI requests
2012-07-17 22:55:40 -07:00
fd95159837
INPUT/OUTPUT orderring swapped
2012-07-12 18:16:57 -07:00
7408c9ab69
removing wires
2012-05-24 10:42:39 -07:00
622a801bb1
Refactored cpu/cache interface to use nested bundles
2012-05-02 11:54:28 -07:00
7f254d9670
refine FP bugfixes
2012-04-01 14:52:33 -07:00
c7c35322c2
two bug fixes to fpu
2012-03-31 22:23:51 -07:00
a70f0414fa
fix a workaroundable bug
2012-03-26 20:51:54 -07:00
86d56ff67b
refactor cpu/i$/d$ into Tile (rather than Top)
2012-03-24 16:57:28 -07:00
54fa6f660d
new supervisor mode
2012-03-24 13:03:31 -07:00
aaed0241af
get rid of vxcptwait
2012-03-21 15:09:04 -07:00
a47eeb9571
retime D$ bypass into beginning of EX stage
2012-03-16 18:35:54 -07:00
b19d783fbd
add vector irq handler
2012-03-14 14:15:28 -07:00
040d62f372
refactored vector exception handling interface
2012-03-13 23:45:34 -07:00
b100544b25
datapath to read out vector state
2012-03-13 23:45:34 -07:00
a1b30282dd
major refactoring on vector exception interface
2012-03-09 01:09:22 -08:00
d4ec7ff4d9
refined vector exception interface
2012-03-03 16:11:54 -08:00
e28a551368
refactor code related to vector exceptions
...
- revisied interfaces
- new instructions
2012-03-03 15:15:00 -08:00
1054cec087
add vec countq interface
2012-03-02 00:43:32 -08:00
8678b3d70c
clean up ioDecoupled/ioPipe interface
2012-03-01 20:48:46 -08:00
bfd0ae125e
upgrade to new rocket/vu memory interface, fix amo nack bug in hellacache
2012-02-26 23:46:51 -08:00
e12b9eae93
remove ext_mem interface
...
hindsight is 20/20
2012-02-26 18:53:39 -08:00
2d04664a98
simplify cpu-cache interface
2012-02-26 18:26:29 -08:00
94ba32bbd3
change package name and sbt project name to rocket
2012-02-25 17:09:26 -08:00
946e0c6e4e
add vector exception infrastructure
2012-02-25 16:37:56 -08:00
3839e3a318
massive refactoring of vector constants
2012-02-25 15:55:36 -08:00
a1600d95db
fix bug related to waddr and wdata in wb stage
...
for the instructions which don't use waddr/wdata for writeback, the contents were getting overwritten by the ll ops
it manifested itself after cp imul were sharing the alu with the vu
2012-02-25 12:21:10 -08:00
4121fb178c
clean up mul/div interface; use VU mul if HAVE_VEC
2012-02-24 19:22:35 -08:00
