riscv/rocket-chip
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Author SHA1 Message Date
Howard Mao c831a0a4e5 use scala firrtl instead of stanza firrtl 2016-03-30 19:35:25 -07:00
Howard Mao be612e3843 bump rocket and uncore 2016-03-30 19:23:19 -07:00
Howard Mao c081a36893 Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter" 
This reverts commit 5378f79b50.
 2016-03-30 19:06:32 -07:00
Howard Mao e77900f540 Revert "switch back to Chisel2 for verilog build for now" 
This reverts commit 3673365b08.
 2016-03-30 19:00:38 -07:00
Howard Mao 8e601f26e1 switch back to the correct chisel3 and firrtl branches 2016-03-30 18:59:33 -07:00
Howard Mao 1e03408323 get rid of mt benchmark suite 2016-03-29 20:16:07 -07:00
Howard Mao cf716fea58 fix mm_dramsim2 2016-03-29 20:16:07 -07:00
Howard Mao 3673365b08 switch back to Chisel2 for verilog build for now 2016-03-29 20:16:07 -07:00
Howard Mao 265a82427e add DefaultL2Config and DualCoreConfig to travis 2016-03-29 20:16:07 -07:00
Howard Mao ad93e0226d Changes to prepare for switch to TileLink interconnect 
We are planning on switching to a TileLink interconnect throughout and
convert to AXI only on the very edge. Therefore, we need to get rid of
all the existing AXI masters other than the TileLink to AXI converter.

* Get rid of DMA engine for now
* Connect RTC to TileLink interconnect instead of AXI interconnect
 2016-03-29 20:16:07 -07:00
Howard Mao 38649bd4c1 some edits to groundtest regression tests 2016-03-29 20:16:07 -07:00
Howard Mao 9b9c662952 fix w_last wire 2016-03-29 20:16:07 -07:00
Howard Mao 2b61f28356 don't test DMA controller for now 2016-03-29 20:16:07 -07:00
Howard Mao e1a03cc9ac fix issue with partial writemasks 2016-03-29 20:16:07 -07:00
Howard Mao e90a9dfb2b make taking max of multiple integers in config a bit easier 2016-03-16 14:35:08 -07:00
Howard Mao 3c9e63f5a5 don't make HTIF clock divider tied to backup memory 2016-03-09 14:58:20 -08:00
Howard Mao 5e145515e1 fix some Chisel assertions 2016-03-02 14:50:49 -08:00
Howard Mao 760893e448 add makefile for float_fix and comlog tools 2016-02-29 11:24:53 -08:00
Howard Mao be8a411f9c get rid of axe submodule and move toaxe.py script to scripts 2016-02-29 10:59:19 -08:00
Howard Mao 8a877fa620 Add Matthew Naylor's trace generator and AXE scripts 2016-02-24 14:39:11 -08:00
Howard Mao 8c02cb09ca some additions to Travis and fixes for Testing 2016-02-23 23:37:29 -08:00
Howard Mao 4fedd180ee bump uncore and groundtest 2016-02-19 23:31:09 -08:00
Howard Mao 85cc632d5d fix emulator debug build 2016-02-19 23:13:57 -08:00
Howard Mao 5e4a02038c move FPGA AXI to HTIF converter into Chisel module 2016-02-19 13:53:31 -08:00
Howard Mao 9fb2216548 get rid of unused external mmio port 2016-02-10 21:49:02 -08:00
Howard Mao 4b95374f0c bump rocket for bug fixes 2016-02-10 11:12:48 -08:00
Howard Mao 72a876bfba add NASTI to TL converter 2016-02-10 11:12:39 -08:00
Howard Mao 06c3f9b655 Rocket Chip fixes in response to lowRISC team's comments 
* DMA frontend-backend communication tunneled over TileLink/AXI
 * Split MMIO and Mem requests in l1tol2net instead of in AXI interconnect
 * Don't make NIOMSHRs configurable. Fixed at 1.
 * Connect accelerator-internal CSRs into the CSR file
 * Make mtvec register configurable and writeable
 2016-02-02 13:14:52 -08:00
Howard Mao ff79a44eb0 move some utility code from uncore to junctions 2016-01-21 15:39:09 -08:00
Howard Mao 04fd407c3e bump rocket submodule pointer 2016-01-15 15:29:23 -08:00
Howard Mao 3b4b7126ed Chisel3 compile-time deprecations should be runtime errors 2016-01-14 15:12:41 -08:00
Howard Mao 33aa64212d fix more Chisel3 deprecations 2016-01-14 15:06:30 -08:00
Howard Mao c06884b78c lowercase SMI to Smi 2016-01-11 17:44:10 -08:00
Howard Mao 806e40d19b implement DMA streaming functionality 2016-01-07 19:26:15 -08:00
Howard Mao 2f71a3da5a bump up submodule commits to merge commits 
Github's PR system doesn't work so well with submodules, since it always
creates merge commits. We should probably avoid using it in the future.
 2015-12-22 08:09:24 -08:00
Howard Mao 0f51ca4c10 Merge pull request #35 from ucb-bar/dma 
Implement DMA unit
 2015-12-22 10:33:59 -05:00
Howard Mao 8190bf6e18 implement DMA unit 2015-12-16 21:27:48 -08:00
Howard Mao 1a272677ca more fixes to L2 cache 2015-12-16 21:06:39 -08:00
Howard Mao 560fdc19a8 add PLRU replacement option to L2 cache 2015-12-16 10:24:57 -08:00
Howard Mao 7ad9deeaee Fix issues with request merging in L2 cache and add regression tests 
In addition to the fix, there are several additions to the
RegressionTest module. The set of regressions is now parameterized and
split into ones for the cache and ones for the broadcast hub.
 2015-12-15 23:02:15 -08:00
Howard Mao 0c91e00676 move GroundTest configs to a separate file 2015-12-06 03:01:05 -08:00
Howard Mao 4f5dabcda2 add SCR file to device tree 2015-12-05 00:28:58 -08:00
Howard Mao 6fc1e92708 add option to print cycle count regardless of exit status 2015-12-04 12:04:13 -08:00
Howard Mao f35b83d3ca allow configuration of rocket ICache buffering 2015-12-02 17:18:39 -08:00
Howard Mao ebf2417a32 rocc-fpu-port merged into master for rocket 2015-12-02 09:02:43 -08:00
Howard Mao cdc476a370 change Rocc parameterization 2015-12-01 17:56:09 -08:00
Howard Mao c8c68e75bb base NGenerators on NTiles, not the other way around 2015-12-01 15:26:09 -08:00
Howard Mao e4043570bd bump groundtest and hardfloat 2015-11-30 18:06:15 -08:00
Howard Mao 40d68406d6 use xlen parameter for ALU 2015-11-30 18:04:44 -08:00
Howard Mao 23f0756978 implement support for multiple RoCC accelerators 2015-11-26 12:49:04 -08:00
Howard Mao ec6bfde9a3 fix WritebackUnit issue in uncore 2015-11-21 16:11:22 -08:00
Howard Mao 9d50f37289 fix unused set issue for multiple L2 cache banks 2015-11-20 23:26:28 -08:00
Howard Mao ad3b7fd0e1 adjust CacheFillTest configuration 2015-11-19 10:52:14 -08:00
Howard Mao 4806f72b08 add CacheFillTest to check L2 conflict misses 2015-11-19 00:16:28 -08:00
Howard Mao 3514b6eb87 add some more useful configurations 2015-11-18 22:11:17 -08:00
Howard Mao 379d43d5f4 make MultiChannel routing more performant 2015-11-18 22:11:17 -08:00
Howard Mao a1063bad54 fix issues with non-allocating put/get 2015-11-12 15:54:34 -08:00
Howard Mao 6ddf81090b didn't mean to turn off GenerateCached in last commit 2015-11-11 17:39:08 -08:00
Howard Mao 11f0b3d8db restore old L2 cache AcquireTransactor configuration 2015-11-11 17:10:58 -08:00
Howard Mao 31da692ccc default to single tile in WithMemtest 2015-11-11 14:54:13 -08:00
Howard Mao 55581195eb add groundtest submodule for simple memory testing 2015-11-11 14:33:02 -08:00
Howard Mao 149480411e make sure ClientTileLinkEnqueuer uses the correct parameters 2015-11-10 16:09:19 -08:00
Howard Mao 51f128ec74 actually use backendBuffering in front of unwrapper/converter chain 2015-11-09 11:50:18 -08:00
Howard Mao cb0c2df051 update fpga-zynq 2015-11-05 10:50:13 -08:00
Howard Mao 42e7067400 bump uncore 2015-11-05 10:49:25 -08:00
Howard Mao bbf14ddc01 use definitions in consts header whenever possible 2015-11-05 10:48:32 -08:00
Howard Mao fb501e75c0 fixes for sub-block TL requests in uncore 2015-11-05 10:48:32 -08:00
Howard Mao 7b252d8f89 get rid of now-unnecessary bits in MIF tag 2015-11-05 10:48:32 -08:00
Howard Mao ba5a6af05c correctly stripe data across memory channels in simulation 2015-11-05 10:48:32 -08:00
Howard Mao dcef020ca0 get multichannel simulation working in emulator 2015-11-05 10:48:32 -08:00
Howard Mao 04d92dddbd add back decoupled NASTI connection at edge of RocketChip 2015-11-05 10:48:32 -08:00
Howard Mao 9dabcab9c2 Get rid of MemIO in Top and replace with AXI throughout 2015-11-05 10:48:32 -08:00
Howard Mao eb62ff6a50 add queues between Nasti -> TL converter and Nasti interconnect 2015-10-26 14:15:25 -07:00
Howard Mao f37938e4de implement MultiChannel routing 2015-10-26 14:15:25 -07:00
Howard Mao c3a7dcf0ab fix missing cde library dependencies in submodules 2015-10-23 15:05:19 -07:00
Howard Mao 21f342ad42 fix typo causing L2 cache configuration to fail 2015-10-21 13:37:33 -07:00
Howard Mao d5a75fd113 accidentally committed some code I didn't mean to in Rocket 2015-10-21 09:21:54 -07:00
Howard Mao 693a4ae00e fix some more memory system bugs 2015-10-20 23:29:59 -07:00
Howard Mao c311c9938e nitpicky declaration move 2015-10-20 21:10:54 -07:00
Howard Mao 4346111d2a fix remaining vsim harness typo 2015-10-19 20:20:14 -07:00
Howard Mao 896aa892d1 bump uncore for TL -> NASTI converter fix 2015-10-19 15:31:59 -07:00
Howard Mao c4117eb9a2 make sure TL parameters change properly throughout 
* Outermost TL parameters should have the width set to be the same as the
   MIF data width.
 * Broadcast Hub and Narrower, which use different sets of TL parameters
   should use the proper set of parameters at each interface
 2015-10-14 18:03:39 -07:00
Howard Mao a44e054c77 add support for different TileLink and MIF data widths 2015-10-13 12:46:23 -07:00
Howard Mao a76f0bf8fb fix involuntary release bug in rocket ProbeUnit 2015-09-30 17:26:48 -07:00
Howard Mao 353b00c8a1 revert some Chisel3-related changes and fix tlb bugs 2015-09-26 22:08:06 -07:00
Howard Mao c517d9f6e3 fix htif emulator constructor in vcs_main 2015-09-25 17:21:09 -07:00
Howard Mao 7b0167b92e make sure SCR and PCR data width matches xLen 2015-09-25 12:13:22 -07:00
Howard Mao 0e67d824b4 fix NASTI interconnect bug 2015-09-25 12:12:34 -07:00
Howard Mao 0d763524ef make sure conf address map scales with number of cores 2015-09-25 09:41:19 -07:00
Howard Mao 5e3f9115d3 make sure HTIF mem_mb doesn't exceed MMIOBase 2015-09-25 09:02:35 -07:00
Howard Mao c20ed350a0 even more Chisel3 compatability changes 2015-09-24 17:55:41 -07:00
Howard Mao 1c0111cc70 uncore merge commit 2015-09-24 17:10:45 -07:00
Howard Mao 8d4d8680bf replace NASTIMasterIO and NASTISlaveIO with NASTIIO 2015-09-24 16:59:13 -07:00
Howard Mao 4a85c5a510 pull in hardfloat fixes 2015-09-24 16:58:49 -07:00
Howard Mao 38a9b23ce7 add a flag to only log and dump after a certain number of cycles 2015-09-22 10:32:31 -07:00
Howard Mao 4496e8d4e2 make sure htif_emulator properly sets memory size 2015-09-22 10:32:31 -07:00
Howard Mao 56ecdff52d Implement NASTI-based Mem/IO interconnect 2015-09-22 10:32:31 -07:00