riscv/rocket-chip
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Author SHA1 Message Date
Yunsup Lee
caf89baeb7 update zscale 2015-07-23 13:59:45 -07:00
Andrew Waterman
ae73e3a997 Only instantiate div/sqrt unit if requested 2015-07-22 22:18:18 -07:00
Andrew Waterman
e9433ee01e Minor cleanup 2015-07-22 17:38:08 -07:00
Andrew Waterman
b4e4ceed3d Factor out some more hazard detection code 2015-07-22 15:52:13 -07:00
Andrew Waterman
bd785e7d19 Factor out common hazard detection code 2015-07-22 15:46:20 -07:00
Henry Cook
bd4ff35a4b Upgrade sbt to 0.13.8, simplify build.scala Tasks, generate tests from TestGenerator App, set addons with env variable ROCKETCHIP_ADDONS 2015-07-22 11:49:10 -07:00
Andrew Waterman
cc447c8110 Refactor pipeline RTL (merge ctrl + dpath into rocket) 2015-07-21 17:10:56 -07:00
Andrew Waterman
25e1412a33 Merge pull request #11 from ucb-bar/regression-fixes 
Regression script fixes
 2015-07-20 12:58:54 -07:00
Palmer Dabbelt
d6b29ca9cc Run regression with bash's "-ex" mode 
This causes every command to be echo'd to stderr, and any failing
command will fail the whole script.  Without this the regression
script will always pass.
 2015-07-20 12:21:19 -07:00
Palmer Dabbelt
9bbecffbb8 Have regression run "make" before "make run-asm-tests" 
I'm seeing some odd behavior where "make run-asm-tests" actually does
nothing.  This works around the issue.
 2015-07-20 12:20:32 -07:00
Yunsup Lee
a99b1e3a01 append config name to generated Makefrag filename 2015-07-17 12:34:49 -07:00
Yunsup Lee
777facf91e update tools 2015-07-17 12:33:19 -07:00
Yunsup Lee
e7802825c3 add Zscale testing 2015-07-17 12:02:02 -07:00
Andrew Waterman
ac6e73e317 Add Wire() wrap 2015-07-15 20:24:18 -07:00
Andrew Waterman
3c0475e08b Add Wire() wrap 2015-07-15 20:24:03 -07:00
Andrew Waterman
2d6b3b2331 Don't use clone 2015-07-15 18:06:27 -07:00
Andrew Waterman
276f53b652 Delete BigMem; it's not used anymore 2015-07-15 17:41:47 -07:00
Andrew Waterman
5b7f3c3006 Don't use clone 2015-07-15 17:30:50 -07:00
Henry Cook
1e977d12f2 Update README.md 2015-07-15 16:25:04 -07:00
Henry Cook
f5b3649b73 Merge commit 'd819fb28c3370747475d7c5f4b641723cab1fd0c' into rocc-fpu-port 2015-07-15 15:29:56 -07:00
Andrew Waterman
15cec0eab7 Vec(Reg) -> Reg(Vec) 2015-07-15 12:44:54 -07:00
Andrew Waterman
be2ff6dec7 Vec(Reg) -> Reg(Vec) 2015-07-15 12:33:46 -07:00
Yunsup Lee
4c7c3f5bb2 add test generate for ZscaleTop 2015-07-14 16:26:28 -07:00
Yunsup Lee
d6df479870 move 'include /Makefrag' out of top-level Makefrag 2015-07-14 16:13:32 -07:00
Henry Cook
76046c52fe Cleanup testing rv64uf 2015-07-13 18:58:58 -07:00
Henry Cook
186e32a546 Merge pull request #9 from ucb-bar/param-based-makefrags 
Param-based makefrag generation
 2015-07-13 15:51:28 -07:00
Henry Cook
302cd3e638 Added BuildZscale param for use in Top and makefrag generation 2015-07-13 15:46:42 -07:00
Henry Cook
407d8e473e first cut at parameter-based testing 2015-07-13 14:54:26 -07:00
Andrew Waterman
a78e28523c Chisel3: Don't mix Mux types 2015-07-11 14:06:08 -07:00
Andrew Waterman
e76a9d3493 Chisel3: Don't mix Mux types 2015-07-11 14:05:39 -07:00
Andrew Waterman
5dc3da008e Use Chisel3 SeqMem construct 2015-07-11 13:36:26 -07:00
Andrew Waterman
3233867390 Use Chisel3 SeqMem construct 2015-07-11 13:34:57 -07:00
Henry Cook
4e4015089d rename Configs source 2015-07-09 15:04:11 -07:00
Henry Cook
3573fcdf2d bump uncore 2015-07-09 14:42:38 -07:00
Henry Cook
fb91e3e1ab minor metadata API update (0.3.3) 2015-07-09 14:36:09 -07:00
Henry Cook
80ad1eac70 Update README.md 2015-07-08 19:05:18 -07:00
Yunsup Lee
09e29e8fe0 add zscale 
only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
 2015-07-07 20:38:47 -07:00
Yunsup Lee
e6a13cdeba New machine-mode timer facility 
Mirroring Andrew's commit to reference-chip
 2015-07-07 17:26:07 -07:00
Henry Cook
4fbb0f80ff Added some multicore/multibanks named ChiselConfigs 2015-07-06 18:21:06 -07:00
Henry Cook
854fd64fba Added optional Makefile includes for private chip repos 2015-07-06 17:15:27 -07:00
Henry Cook
5ed2899e56 Merge pull request #10 from wsong83/fix 
L1 D$ writeback unit, reduce re-read data array
 2015-07-06 15:18:49 -07:00
Andrew Waterman
5362e2bbbd New machine-mode timer facility 2015-07-05 16:38:49 -07:00
Andrew Waterman
55059632c4 Temporarily use HTIF to push RTC value to cores 2015-07-05 16:19:39 -07:00
Henry Cook
d3ccec1044 Massive update containing several months of changes from the now-defunct private chip repo. 
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
 2015-07-02 14:43:30 -07:00
Henry Cook
d7cb60e8fa L2 WritebackUnit bug fix 2015-07-02 13:52:40 -07:00
Scott Beamer
12d8d8c5e3 Merge pull request #8 from seldridge/master 
Fix FPGA/VLSI Mem Gen for Python 2 and 3 Environments
 2015-06-28 08:54:24 -05:00
Schuyler Eldridge
b4cd8c5981 Fix vlsi_mem_gen for Python 2 or 3 2015-06-25 12:48:31 -07:00
Schuyler Eldridge
a42832fc70 Fix fpga_mem_gen for Python 2 and 3 Environments 
Two quick fixes that enable fpga_mem_gen to work with either Python 2 or
Python 3:
* Change an `xrange` instance to `range`
* Wrap the arguments of a bare `print` in parentheses
 2015-06-25 11:03:33 -07:00
Andrew Waterman
b4e38192a1 Fix (?) L2$ miss bug 
The victim's metadata was incorrectly used for the new line.
 2015-06-24 18:01:56 -07:00
Andrew Waterman
5e009ecc75 Fix an apparently benign PC sign-extension bug 2015-06-11 16:08:39 -07:00