Yunsup Lee
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516a64f576
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commit vec=true
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2013-01-22 20:24:33 -08:00 |
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Henry Cook
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b5ccdab514
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changed val names in hub to match new tilelink names
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2013-01-22 20:09:21 -08:00 |
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Henry Cook
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bb5c465bb3
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Switched back to old, better-tested hub on master
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2013-01-22 19:57:31 -08:00 |
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Henry Cook
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5b82d72eb7
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New TileLink bundle names
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2013-01-21 17:19:07 -08:00 |
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Henry Cook
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6b00e7ff74
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New TileLink bundle names
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2013-01-21 17:18:23 -08:00 |
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Henry Cook
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c211d74e95
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New TileLink names
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2013-01-21 17:17:26 -08:00 |
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Henry Cook
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72bba81a76
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now using single-ported coherence master
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2013-01-16 23:58:24 -08:00 |
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Henry Cook
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fb2644760f
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single-ported coherence master
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2013-01-16 23:57:35 -08:00 |
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Henry Cook
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e33648532b
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Refactored packet headers/payloads
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2013-01-15 15:57:06 -08:00 |
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Henry Cook
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f7c0152409
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Refactored packet headers/payloads
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2013-01-15 15:52:47 -08:00 |
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Henry Cook
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a2fa3fd04d
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Refactored packet headers/payloads
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2013-01-15 15:50:37 -08:00 |
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Henry Cook
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a922b60152
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Merge branch 'master' of github.com:ucb-bar/reference-chip into network-refactor
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2013-01-07 14:23:49 -08:00 |
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Henry Cook
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f2cef8d8d2
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new IO names, set val/rdy low for unused network inputs, add src/dst setting for tiles, incoherent sig out of tilelink, bump chisel/rocket/uncore
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2013-01-07 14:19:55 -08:00 |
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Henry Cook
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f836bd93e1
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Bugfix in crossbar ready sigs, added adapter for old hub, removed incoherent sig from tilelink
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2013-01-07 14:01:39 -08:00 |
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Henry Cook
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418e3fdf50
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Bugfix in crossbar ready sigs, added adapter for old hub, removed incoherent sig from tilelink
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2013-01-07 13:57:48 -08:00 |
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Henry Cook
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e1225c5114
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standardize IO naming convention
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2013-01-07 13:41:36 -08:00 |
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Henry Cook
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261e14f831
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Refactored uncore conf
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2013-01-07 13:41:36 -08:00 |
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Andrew Waterman
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bbd010750f
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add missing #include
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2013-01-06 04:53:40 -08:00 |
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Andrew Waterman
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fd727bf8aa
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add some of the zedboard fpga infrastructure
you can elaborate the RTL in fpga/build/vcs-sim-rtl, but there's no harness
for VCS simulation yet.
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2013-01-06 03:58:10 -08:00 |
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Andrew Waterman
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03df2c3766
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update .gitignores
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2013-01-06 03:58:10 -08:00 |
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Andrew Waterman
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78868f6075
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add config option to trade mul/div area for speed
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2013-01-06 03:47:17 -08:00 |
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Andrew Waterman
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ce9f4881d2
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remove broken multiplier early out
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2013-01-06 03:47:00 -08:00 |
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Henry Cook
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d0805359a5
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Refactored uncore conf
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2012-12-13 11:46:29 -08:00 |
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Henry Cook
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400d48e3de
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Refactored uncore conf
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2012-12-13 11:39:14 -08:00 |
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Henry Cook
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1d7f1a8182
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Removed dummy tile instances
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2012-12-12 16:44:03 -08:00 |
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Henry Cook
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0e73cc8c12
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Removed dummy tile instances
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2012-12-12 16:41:21 -08:00 |
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Henry Cook
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177909c955
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Initial version of phys/log network compiles
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2012-12-12 11:15:10 -08:00 |
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Henry Cook
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6d61baa6cd
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Initial version of phys/log network compiles
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2012-12-12 11:08:50 -08:00 |
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Henry Cook
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f359518e52
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wip: new network classes
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2012-12-12 11:08:50 -08:00 |
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Andrew Waterman
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05f19b21d0
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merge multiplier and divider
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2012-12-12 02:22:47 -08:00 |
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Andrew Waterman
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c921fc34a9
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merge ALU left and right shifters
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2012-12-12 02:22:34 -08:00 |
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Henry Cook
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be4e5b8327
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Initial version of phys/log network compiles
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2012-12-12 00:06:14 -08:00 |
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Henry Cook
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8d69f9b41c
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Initial version of phys/log network compiles
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2012-12-12 00:05:28 -08:00 |
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Andrew Waterman
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f5c53ce35d
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add ecc support to d$ data rams
i haven't injected errors yet; it may well be incorrect.
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2012-12-11 15:58:53 -08:00 |
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Yunsup Lee
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98c0ea9875
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push rocket, tests, and vt-libs
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2012-12-07 16:59:15 -08:00 |
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Andrew Waterman
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3f59e439ef
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fix d$ tag raw hazard
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2012-12-07 15:14:20 -08:00 |
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Henry Cook
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12caa55dc7
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wip: new network classes
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2012-12-06 18:51:30 -08:00 |
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Andrew Waterman
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e9752f1d72
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pipeline host pcr access
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2012-12-06 14:22:07 -08:00 |
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Andrew Waterman
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10a6a42a4a
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make vlsi use dram model by default
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2012-12-06 03:13:45 -08:00 |
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Andrew Waterman
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4dda38204f
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fix d$ reset bug
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2012-12-06 03:13:22 -08:00 |
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Andrew Waterman
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290d3d226c
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fix AMO and store bypass bugs
thanks, torture tester
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2012-12-06 02:07:52 -08:00 |
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Andrew Waterman
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aae7a67781
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fix llc refill/writeback bugs
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2012-12-06 02:07:03 -08:00 |
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Andrew Waterman
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d911e635d6
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simplify c++ memory models; support +dramsim flag
works for both vlsi and emulator
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2012-12-04 07:04:26 -08:00 |
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Andrew Waterman
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50e9d952e8
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don't initiate llc refill until writeback drains
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2012-12-04 06:57:53 -08:00 |
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Andrew Waterman
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4608660f6e
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torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
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2012-12-04 05:57:53 -08:00 |
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Andrew Waterman
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5dfb388f03
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update to newest rocket
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2012-11-27 02:43:31 -08:00 |
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Andrew Waterman
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90cae54ac4
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fix D$ read/write concurrency bug
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2012-11-27 02:42:27 -08:00 |
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Andrew Waterman
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9c857b83f0
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refactor PCR file
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2012-11-27 01:28:06 -08:00 |
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Andrew Waterman
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ea7029484e
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update to latest rocket
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2012-11-26 20:57:12 -08:00 |
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Andrew Waterman
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8103676b37
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reduce physical address space to 4GB
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2012-11-26 20:54:56 -08:00 |
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