new IO names, set val/rdy low for unused network inputs, add src/dst setting for tiles, incoherent sig out of tilelink, bump chisel/rocket/uncore
This commit is contained in:
Henry Cook
parent
d0805359a5
commit
f2cef8d8d2
2
chisel
2
chisel
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@ -1 +1 @@
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Subproject commit 2387c2d41ba2239c8939c1a0819201db300297d5
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Subproject commit 713523f92973826feaa404044c6b2f6d8bd0e615
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@ -1 +1 @@
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Subproject commit fbe177a2c549bf3ecdfeda74f8ceb81ef96232b8
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Subproject commit f6548d6cb5ff1b62077e8fd52ab9834fdabd8037
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@ -85,8 +85,8 @@ class CrossbarToHubShim[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkC
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io.in.ready := io.out.ready
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}
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class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgent])(implicit conf: LogicalNetworkConfiguration) extends LogicalNetwork[TileLink](endpoints)(conf) {
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type TileLinkType = TileLink
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class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgent])(implicit conf: LogicalNetworkConfiguration) extends LogicalNetwork[TileLinkIO](endpoints)(conf) {
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type TileLinkType = TileLinkIO
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val io = Vec(endpoints.map(_ match { case t:ClientCoherenceAgent => {(new TileLinkType).flip}; case h:MasterCoherenceAgent => {new TileLinkType}})){ new TileLinkType }
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//If we allow all physical networks to be identical, we can use
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@ -106,7 +106,7 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgent])(implicit conf
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endpoints.zip(io).zipWithIndex.map{ case ((end, io), id) => {
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val logNetIOSubBundles = io.getClass.getMethods.filter( x =>
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classOf[LogicalNetworkIO[Data]].isAssignableFrom(x.getReturnType)).zipWithIndex
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val tileProducedSubBundles = logNetIOSubBundles.filter( x =>
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val tileProducedSubBundles = logNetIOSubBundles.filter( x => // filter -> parition?
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classOf[TileIO[Data]].isAssignableFrom(x._1.getReturnType)).map{ case (m,i) =>
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(m.invoke(io).asInstanceOf[TileIO[Data]],i) }
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val hubProducedSubBundles = logNetIOSubBundles.filter( x =>
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@ -114,16 +114,24 @@ class ReferenceChipCrossbarNetwork(endpoints: Seq[CoherenceAgent])(implicit conf
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(m.invoke(io).asInstanceOf[HubIO[Data]],i) }
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end match {
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case x:ClientCoherenceAgent => {
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tileProducedSubBundles.foreach{ case (sl,i) =>
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physicalNetworks(i).io.in(id) <> TileToCrossbarShim(sl) }
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hubProducedSubBundles.foreach{ case (sl,i) =>
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sl <> CrossbarToHubShim(physicalNetworks(i).io.out(id)) }
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tileProducedSubBundles.foreach{ case (sl,i) => {
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physicalNetworks(i).io.in(id) <> TileToCrossbarShim(sl)
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physicalNetworks(i).io.out(id).ready := Bool(false)
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}}
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hubProducedSubBundles.foreach{ case (sl,i) => {
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sl <> CrossbarToTileShim(physicalNetworks(i).io.out(id))
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physicalNetworks(i).io.in(id).valid := Bool(false)
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}}
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}
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case y:MasterCoherenceAgent => {
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hubProducedSubBundles.foreach{ case (sl,i) =>
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physicalNetworks(i).io.in(id) <> HubToCrossbarShim(sl) }
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tileProducedSubBundles.foreach{ case (sl,i) =>
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sl <> CrossbarToTileShim(physicalNetworks(i).io.out(id)) }
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hubProducedSubBundles.foreach{ case (sl,i) => {
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physicalNetworks(i).io.in(id) <> HubToCrossbarShim(sl)
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physicalNetworks(i).io.out(id).ready := Bool(false)
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}}
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tileProducedSubBundles.foreach{ case (sl,i) => {
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sl <> CrossbarToHubShim(physicalNetworks(i).io.out(id))
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physicalNetworks(i).io.in(id).valid := Bool(false)
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}}
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}
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}
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}}
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@ -192,8 +200,9 @@ class OuterMemorySystem(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent
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{
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implicit val lnconf = conf.ln
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val io = new Bundle {
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val tiles = Vec(conf.ln.nTiles) { new TileLink }.flip
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val htif = new TileLink().flip
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val tiles = Vec(conf.ln.nTiles) { new TileLinkIO }.flip
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val htif = (new TileLinkIO).flip
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val incoherent = Vec(conf.ln.nTiles) { Bool() }.asInput
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val mem_backup = new ioMemSerialized(htif_width)
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val mem_backup_en = Bool(INPUT)
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val mem = new ioMemPipe
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@ -206,22 +215,30 @@ class OuterMemorySystem(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent
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nTiles = conf.ln.nTiles+1)
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val chWithHtifConf = conf.copy(ln = lnWithHtifConf)
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require(tileEndpoints.length == lnWithHtifConf.nTiles)
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val hub = new CoherenceHubBroadcast()(chWithHtifConf)
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//val hub = new CoherenceHubBroadcast()(chWithHtifConf)
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val llc_tag_leaf = Mem(1024, seqRead = true) { Bits(width = 72) }
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val llc_data_leaf = Mem(4096, seqRead = true) { Bits(width = 64) }
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val llc = new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf)
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val mem_serdes = new MemSerdes(htif_width)
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val testNet = new ReferenceChipCrossbarNetwork(List(hub)++tileEndpoints)(lnWithHtifConf)
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val testHub = new CoherenceHubBroadcast()(chWithHtifConf)
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val testAdapter = new CoherenceHubAdapter()(lnWithHtifConf)
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val testNet = new ReferenceChipCrossbarNetwork(List(testHub)++tileEndpoints)(lnWithHtifConf)
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testNet.io(0) <> testAdapter.io.net
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testHub.io.tiles <> testAdapter.io.hub
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for (i <- 0 until conf.ln.nTiles) {
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hub.io.tiles(i) <> io.tiles(i)
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for (i <- 1 to conf.ln.nTiles) {
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//hub.io.tiles(i) <> io.tiles(i)
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testNet.io(i) <> io.tiles(i-1)
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testHub.io.incoherent(i-1) := io.incoherent(i-1)
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}
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hub.io.tiles(conf.ln.nTiles) <> io.htif
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//hub.io.tiles(conf.ln.nTiles) <> io.htif
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testNet.io(conf.ln.nTiles+1) <> io.htif
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testHub.io.incoherent(conf.ln.nTiles) := Bool(true)
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llc.io.cpu.req_cmd <> Queue(hub.io.mem.req_cmd)
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llc.io.cpu.req_data <> Queue(hub.io.mem.req_data, REFILL_CYCLES)
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hub.io.mem.resp <> llc.io.cpu.resp
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llc.io.cpu.req_cmd <> Queue(testHub.io.mem.req_cmd)
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llc.io.cpu.req_data <> Queue(testHub.io.mem.req_data, REFILL_CYCLES)
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testHub.io.mem.resp <> llc.io.cpu.resp
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// mux between main and backup memory ports
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val mem_cmdq = (new Queue(2)) { new MemReqCmd }
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@ -250,13 +267,14 @@ class Uncore(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent])(implicit
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{
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implicit val lnconf = conf.ln
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val io = new Bundle {
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val debug = new ioDebug()
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val host = new ioHost(htif_width)
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val debug = new DebugIO()
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val host = new HostIO(htif_width)
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val mem_backup = new ioMemSerialized(htif_width)
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val mem_backup_en = Bool(INPUT)
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val mem = new ioMemPipe
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val tiles = Vec(conf.ln.nTiles) { new TileLink }.flip
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val htif = Vec(conf.ln.nTiles) { new ioHTIF(conf.ln.nTiles) }.flip
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val tiles = Vec(conf.ln.nTiles) { new TileLinkIO }.flip
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val htif = Vec(conf.ln.nTiles) { new HTIFIO(conf.ln.nTiles) }.flip
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val incoherent = Vec(conf.ln.nTiles) { Bool() }.asInput
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}
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val htif = new rocketHTIF(htif_width)
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@ -265,6 +283,7 @@ class Uncore(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent])(implicit
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val outmemsys = new OuterMemorySystem(htif_width, tileEndpoints++List(htif))
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outmemsys.io.tiles <> io.tiles
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outmemsys.io.htif <> htif.io.mem
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outmemsys.io.incoherent <> io.incoherent
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io.mem <> outmemsys.io.mem
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outmemsys.io.mem_backup_en <> io.mem_backup_en
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@ -292,9 +311,9 @@ class Uncore(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent])(implicit
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io.host.clk_edge := Reg(io.host.clk && !Reg(io.host.clk))
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}
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class ioTop(htif_width: Int) extends Bundle {
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val debug = new rocket.ioDebug();
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val host = new rocket.ioHost(htif_width);
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class TopIO(htif_width: Int) extends Bundle {
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val debug = new rocket.DebugIO
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val host = new rocket.HostIO(htif_width);
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val mem_backup_en = Bool(INPUT)
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val in_mem_ready = Bool(OUTPUT)
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val in_mem_valid = Bool(INPUT)
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@ -330,13 +349,13 @@ class Top extends Component {
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implicit val lnConf = LogicalNetworkConfiguration(NTILES+1, log2Up(NTILES)+1, 1, NTILES)
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implicit val chConf = CoherenceHubConfiguration(co, lnConf)
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val io = new ioTop(HTIF_WIDTH)
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val io = new TopIO(HTIF_WIDTH)
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val resetSigs = Vec(NTILES){ Bool() }
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val ic = ICacheConfig(128, 2, co, ntlb = 8, nbtb = 16)
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val dc = DCacheConfig(128, 4, co, ntlb = 8,
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nmshr = 2, nrpq = 16, nsdq = 17)
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val rc = RocketConfiguration(NTILES, co, ic, dc,
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val rc = RocketConfiguration(lnConf, co, ic, dc,
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fpu = true, vec = true)
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val tileList = (0 until NTILES).map(r => new Tile(resetSignal = resetSigs(r))(rc))
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val uncore = new Uncore(HTIF_WIDTH, tileList)
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@ -345,6 +364,7 @@ class Top extends Component {
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for (i <- 0 until NTILES) {
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val hl = uncore.io.htif(i)
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val tl = uncore.io.tiles(i)
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val il = uncore.io.incoherent(i)
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resetSigs(i) := hl.reset
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val tile = tileList(i)
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@ -364,7 +384,20 @@ class Top extends Component {
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tile.io.tilelink.probe_req <> Queue(tl.probe_req)
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tl.probe_rep <> Queue(tile.io.tilelink.probe_rep, 1)
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tl.probe_rep_data <> Queue(tile.io.tilelink.probe_rep_data)
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tl.incoherent := hl.reset
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il := hl.reset
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tl.xact_init.header.src := UFix(i)
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tl.xact_init.header.dst := UFix(0)
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tl.xact_init_data.header.src := UFix(i)
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tl.xact_init_data.header.dst := UFix(0)
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tl.probe_rep.header.src := UFix(i)
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tl.probe_rep.header.dst := UFix(0)
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tl.probe_rep_data.header.src := UFix(i)
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tl.probe_rep_data.header.dst := UFix(0)
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tl.xact_finish.header.src := UFix(i)
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tl.xact_finish.header.dst := UFix(0)
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//TODO: What about incoming headers?
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}
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io.host <> uncore.io.host
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2
uncore
2
uncore
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@ -1 +1 @@
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Subproject commit f11638a6c8a6e7f59967d360e99daf49dc4a3151
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Subproject commit c781a3152a34071f7f18afccddf59b0c16c3acee
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