single-ported coherence master
This commit is contained in:
Henry Cook
parent
f7c0152409
commit
fb2644760f
@ -112,11 +112,11 @@ class MasterSourcedIO[T <: Data]()(data: => T) extends DirectionalFIFOIO()(data)
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class TileLinkIO(implicit conf: LogicalNetworkConfiguration) extends Bundle {
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val xact_init = (new ClientSourcedIO){(new LogicalNetworkIO){new TransactionInit }}
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val xact_init_data = (new ClientSourcedIO){(new LogicalNetworkIO){new TransactionInitData }}
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val xact_abort = (new MasterSourcedIO) {(new LogicalNetworkIO){new TransactionAbort }}
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val probe_req = (new MasterSourcedIO) {(new LogicalNetworkIO){new ProbeRequest }}
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val xact_abort = (new MasterSourcedIO){(new LogicalNetworkIO){new TransactionAbort }}
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val probe_req = (new MasterSourcedIO){(new LogicalNetworkIO){new ProbeRequest }}
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val probe_rep = (new ClientSourcedIO){(new LogicalNetworkIO){new ProbeReply }}
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val probe_rep_data = (new ClientSourcedIO){(new LogicalNetworkIO){new ProbeReplyData }}
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val xact_rep = (new MasterSourcedIO) {(new LogicalNetworkIO){new TransactionReply }}
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val xact_rep = (new MasterSourcedIO){(new LogicalNetworkIO){new TransactionReply }}
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val xact_finish = (new ClientSourcedIO){(new LogicalNetworkIO){new TransactionFinish }}
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override def clone = { new TileLinkIO().asInstanceOf[this.type] }
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}
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@ -524,3 +524,347 @@ class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends Co
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}
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}
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abstract class CoherenceAgent(implicit conf: LogicalNetworkConfiguration) extends Component with MasterCoherenceAgent {
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val io = new Bundle {
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val network = (new TileLinkIO).flip
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val incoherent = Vec(conf.nTiles) { Bool() }.asInput
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val mem = new ioMem
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}
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}
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class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends CoherenceAgent()(conf.ln)
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{
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implicit val lnConf = conf.ln
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val co = conf.co
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val trackerList = (0 until NGLOBAL_XACTS).map(new XactTracker(_))
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val p_rep_data_dep_q = (new Queue(NGLOBAL_XACTS)){new TrackerDependency} // depth must >= NPRIMARY
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val x_init_data_dep_q = (new Queue(NGLOBAL_XACTS)){new TrackerDependency} // depth should >= NPRIMARY
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for( i <- 0 until NGLOBAL_XACTS ) {
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val t = trackerList(i)
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t.io.tile_incoherent := io.incoherent.toBits
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t.io.mem_resp.valid := io.mem.resp.valid && (io.mem.resp.bits.tag === UFix(i))
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t.io.mem_resp.bits := io.mem.resp.bits
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}
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io.mem.resp.ready := trackerList.map(_.io.mem_resp.ready).reduce(_||_)
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// Handle transaction initiation requests
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// Only one allocation per cycle
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// Init requests may or may not have data
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val x_init = io.network.xact_init
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val x_init_data = io.network.xact_init_data
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val x_abort = io.network.xact_abort
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val x_dep_deq = x_init_data_dep_q.io.deq
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val s_idle :: s_abort_drain :: s_abort_send :: Nil = Enum(3){ UFix() }
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val abort_state = Reg(resetVal = s_idle)
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val abort_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
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val any_conflict = trackerList.map(_.io.has_conflict).reduce(_||_)
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val all_busy = trackerList.map(_.io.busy).reduce(_&&_)
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val want_to_abort = x_init.valid && (any_conflict || all_busy || (!x_init_data_dep_q.io.enq.ready && co.messageHasData(x_init.bits.payload)))
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val alloc_arb = (new Arbiter(NGLOBAL_XACTS)) { Bool() }
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for( i <- 0 until NGLOBAL_XACTS ) {
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alloc_arb.io.in(i).valid := !trackerList(i).io.busy
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trackerList(i).io.x_init.bits := x_init.bits
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trackerList(i).io.x_init.valid := (abort_state === s_idle) && !want_to_abort && x_init.valid && alloc_arb.io.in(i).ready
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trackerList(i).io.x_init_data.bits := x_init_data.bits
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trackerList(i).io.x_init_data.valid := x_init_data.valid
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trackerList(i).io.x_init_data_dep.bits := x_dep_deq.bits
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trackerList(i).io.x_init_data_dep.valid := x_dep_deq.valid
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}
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val pop_x_init = trackerList.map(_.io.x_init.ready).reduce(_||_)
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x_init.ready := (x_abort.valid && x_abort.ready) || pop_x_init
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x_init_data.ready := (abort_state === s_abort_drain) || trackerList.map(_.io.x_init_data.ready).reduce(_||_)
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x_init_data_dep_q.io.enq.valid := pop_x_init && co.messageHasData(x_init.bits.payload) && (abort_state === s_idle)
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x_init_data_dep_q.io.enq.bits.global_xact_id := OHToUFix(trackerList.map(_.io.x_init.ready))
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x_dep_deq.ready := trackerList.map(_.io.x_init_data_dep.ready).reduce(_||_)
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alloc_arb.io.out.ready := x_init.valid
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// Nack conflicting transaction init attempts
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x_abort.bits.header.dst := x_init.bits.header.src
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x_abort.bits.payload.tile_xact_id := x_init.bits.payload.tile_xact_id
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x_abort.valid := Bool(false)
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switch(abort_state) {
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is(s_idle) {
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when(want_to_abort) {
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abort_state := Mux( co.messageHasData(x_init.bits.payload), s_abort_drain, s_abort_send)
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}
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}
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is(s_abort_drain) { // raises x_init_data.ready below
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when(x_init_data.valid) {
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abort_cnt := abort_cnt + UFix(1)
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when(abort_cnt === ~UFix(0, width = log2Up(REFILL_CYCLES))) {
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abort_state := s_abort_send
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}
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}
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}
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is(s_abort_send) { // nothing is dequeued for now
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x_abort.valid := Bool(true)
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when(x_abort.ready) { // raises x_init.ready
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abort_state := s_idle
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}
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}
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}
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// Handle probe request generation
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val p_req_arb = (new Arbiter(NGLOBAL_XACTS)){(new LogicalNetworkIO){ new ProbeRequest }}
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for( i <- 0 until NGLOBAL_XACTS ) {
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val t = trackerList(i).io
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p_req_arb.io.in(i).bits := t.p_req.bits
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p_req_arb.io.in(i).valid := t.p_req.valid
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t.p_req.ready := p_req_arb.io.in(i).ready
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}
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io.network.probe_req <> p_req_arb.io.out
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// Handle probe replies, which may or may not have data
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val p_rep = io.network.probe_rep
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val p_rep_data = io.network.probe_rep_data
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val idx = p_rep.bits.payload.global_xact_id
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p_rep.ready := trackerList.map(_.io.p_rep.ready).reduce(_||_)
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p_rep_data.ready := trackerList.map(_.io.p_rep_data.ready).reduce(_||_)
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p_rep_data_dep_q.io.enq.valid := p_rep.valid && co.messageHasData(p_rep.bits.payload)
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p_rep_data_dep_q.io.enq.bits.global_xact_id := p_rep.bits.payload.global_xact_id
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p_rep_data_dep_q.io.deq.ready := trackerList.map(_.io.p_rep_data_dep.ready).reduce(_||_)
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for( i <- 0 until NGLOBAL_XACTS ) {
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trackerList(i).io.p_rep_data.valid := p_rep_data.valid
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trackerList(i).io.p_rep_data.bits := p_rep_data.bits
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trackerList(i).io.p_rep_data_dep.valid := p_rep_data_dep_q.io.deq.valid
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trackerList(i).io.p_rep_data_dep.bits := p_rep_data_dep_q.io.deq.bits
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trackerList(i).io.p_rep.valid := p_rep.valid && (idx === UFix(i))
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trackerList(i).io.p_rep.bits := p_rep.bits
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}
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// Reply to initial requestor
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// Forward memory responses from mem to tile or arbitrate to ack
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val x_rep_arb = (new Arbiter(NGLOBAL_XACTS)){(new LogicalNetworkIO){ new TransactionReply }}
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for( i <- 0 until NGLOBAL_XACTS ) {
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val t = trackerList(i).io
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x_rep_arb.io.in(i).bits := t.x_rep.bits
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x_rep_arb.io.in(i).valid := t.x_rep.valid
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t.x_rep.ready := x_rep_arb.io.in(i).ready
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}
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x_rep_arb.io.out.ready := Bool(false)
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io.network.xact_rep.valid := x_rep_arb.io.out.valid
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io.network.xact_rep.bits := x_rep_arb.io.out.bits
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x_rep_arb.io.out.ready := io.network.xact_rep.ready
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when(io.mem.resp.valid) {
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io.network.xact_rep.valid := Bool(true)
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io.network.xact_rep.bits := Vec(trackerList.map(_.io.x_rep.bits)){(new LogicalNetworkIO){new TransactionReply}}(io.mem.resp.bits.tag)
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for( i <- 0 until NGLOBAL_XACTS ) {
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trackerList(i).io.x_rep.ready := (io.mem.resp.bits.tag === UFix(i)) && io.network.xact_rep.ready
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}
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}
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// Free finished transactions
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val finish = io.network.xact_finish
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for( i <- 0 until NGLOBAL_XACTS ) {
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trackerList(i).io.free := finish.valid && (finish.bits.payload.global_xact_id === UFix(i))
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}
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finish.ready := Bool(true)
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// Create an arbiter for the one memory port
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// We have to arbitrate between the different trackers' memory requests
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// and once we have picked a request, get the right write data
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val mem_req_cmd_arb = (new Arbiter(NGLOBAL_XACTS)) { new MemReqCmd() }
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val mem_req_data_arb = (new LockingArbiter(NGLOBAL_XACTS)) { new MemData() }
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for( i <- 0 until NGLOBAL_XACTS ) {
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mem_req_cmd_arb.io.in(i) <> trackerList(i).io.mem_req_cmd
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mem_req_data_arb.io.in(i) <> trackerList(i).io.mem_req_data
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mem_req_data_arb.io.lock(i) <> trackerList(i).io.mem_req_lock
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}
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io.mem.req_cmd <> Queue(mem_req_cmd_arb.io.out)
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io.mem.req_data <> Queue(mem_req_data_arb.io.out)
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}
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class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Component {
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val co = conf.co
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implicit val ln = conf.ln
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val io = new Bundle {
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val x_init = (new FIFOIO){(new LogicalNetworkIO) { new TransactionInit }}.flip
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val x_init_data = (new FIFOIO){(new LogicalNetworkIO) { new TransactionInitData }}.flip
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val p_rep = (new FIFOIO){(new LogicalNetworkIO) { new ProbeReply }}.flip
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val p_rep_data = (new FIFOIO){(new LogicalNetworkIO) { new ProbeReplyData }}.flip
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val free = Bool(INPUT)
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val tile_incoherent = Bits(INPUT, conf.ln.nTiles)
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val p_rep_data_dep = (new FIFOIO) { new TrackerDependency }.flip
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val x_init_data_dep = (new FIFOIO) { new TrackerDependency }.flip
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val mem_resp = (new FIFOIO) { new MemResp }.flip
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val mem_req_cmd = (new FIFOIO) { new MemReqCmd }
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val mem_req_data = (new FIFOIO) { new MemData }
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val mem_req_lock = Bool(OUTPUT)
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val p_req = (new FIFOIO) {(new LogicalNetworkIO) { new ProbeRequest }}
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val x_rep = (new FIFOIO) {(new LogicalNetworkIO) { new TransactionReply }}
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val busy = Bool(OUTPUT)
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val has_conflict = Bool(OUTPUT)
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}
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val s_idle :: s_ack :: s_mem :: s_probe :: s_busy :: Nil = Enum(5){ UFix() }
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val state = Reg(resetVal = s_idle)
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val xact = Reg{ new TransactionInit }
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val init_client_id_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles)))
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//TODO: Will need id reg for merged release xacts
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val init_sharer_cnt_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles)))
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val p_rep_count = if (conf.ln.nTiles == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nTiles)))
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val p_req_flags = Reg(resetVal = Bits(0, width = conf.ln.nTiles))
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val x_needs_read = Reg(resetVal = Bool(false))
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val x_init_data_needs_write = Reg(resetVal = Bool(false))
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val p_rep_data_needs_write = Reg(resetVal = Bool(false))
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val x_w_mem_cmd_sent = Reg(resetVal = Bool(false))
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val p_w_mem_cmd_sent = Reg(resetVal = Bool(false))
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val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES)))
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val mem_cnt_next = mem_cnt + UFix(1)
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val mem_cnt_max = ~UFix(0, width = log2Up(REFILL_CYCLES))
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val p_req_initial_flags = Bits(width = conf.ln.nTiles)
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p_req_initial_flags := Bits(0)
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if (conf.ln.nTiles > 1) {
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// issue self-probes for uncached read xacts to facilitate I$ coherence
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// TODO: this is hackish; figure out how to do it more systematically
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val probe_self = co match {
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case u: CoherencePolicyWithUncached => u.isUncachedReadTransaction(io.x_init.bits.payload)
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case _ => Bool(false)
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}
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val myflag = Mux(probe_self, Bits(0), UFixToOH(io.x_init.bits.header.src(log2Up(conf.ln.nTiles)-1,0)))
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p_req_initial_flags := ~(io.tile_incoherent | myflag)
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}
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val all_x_reps_require_acks = Bool(true)
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io.busy := state != s_idle
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io.has_conflict := co.isCoherenceConflict(xact.addr, io.x_init.bits.payload.addr) && (state != s_idle)
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io.mem_req_cmd.valid := Bool(false)
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io.mem_req_cmd.bits.rw := Bool(false)
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io.mem_req_cmd.bits.addr := xact.addr
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io.mem_req_cmd.bits.tag := UFix(id)
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io.mem_req_data.valid := Bool(false)
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io.mem_req_data.bits.data := UFix(0)
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io.mem_req_lock := Bool(false)
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io.p_req.valid := Bool(false)
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io.p_req.bits.payload.p_type := co.getProbeRequestType(xact.x_type, UFix(0))
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io.p_req.bits.payload.global_xact_id := UFix(id)
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io.p_req.bits.payload.addr := xact.addr
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io.p_req.bits.header.dst := UFix(0)
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io.x_rep.bits.payload.data := io.mem_resp.bits.data
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io.x_rep.bits.payload.x_type := co.getTransactionReplyType(xact.x_type, init_sharer_cnt_)
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io.x_rep.bits.payload.tile_xact_id := xact.tile_xact_id
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io.x_rep.bits.payload.global_xact_id := UFix(id)
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io.x_rep.bits.payload.require_ack := all_x_reps_require_acks
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io.x_rep.bits.header.dst := init_client_id_
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io.x_rep.valid := (io.mem_resp.valid && (UFix(id) === io.mem_resp.bits.tag))
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io.x_init.ready := Bool(false)
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io.x_init_data.ready := Bool(false)
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io.x_init_data_dep.ready := Bool(false)
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io.p_rep.ready := Bool(false)
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io.p_rep_data.ready := Bool(false)
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io.p_rep_data_dep.ready := Bool(false)
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io.mem_resp.ready := io.x_rep.ready
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switch (state) {
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is(s_idle) {
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when( io.x_init.valid ) {
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xact := io.x_init.bits.payload
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init_client_id_ := io.x_init.bits.header.src
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init_sharer_cnt_ := UFix(conf.ln.nTiles) // TODO: Broadcast only
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x_init_data_needs_write := co.messageHasData(io.x_init.bits.payload)
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x_needs_read := co.needsMemRead(io.x_init.bits.payload.x_type, UFix(0))
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p_req_flags := p_req_initial_flags
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mem_cnt := UFix(0)
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p_w_mem_cmd_sent := Bool(false)
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x_w_mem_cmd_sent := Bool(false)
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io.x_init.ready := Bool(true)
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if(conf.ln.nTiles > 1) {
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p_rep_count := PopCount(p_req_initial_flags)
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state := Mux(p_req_initial_flags.orR, s_probe, s_mem)
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} else state := s_mem
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}
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}
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is(s_probe) {
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val curr_p_id = PriorityEncoder(p_req_flags)
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when(p_req_flags.orR) {
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io.p_req.valid := Bool(true)
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io.p_req.bits.header.dst := curr_p_id
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}
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when(io.p_req.ready) {
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p_req_flags := p_req_flags & ~(UFixToOH(curr_p_id))
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}
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when(io.p_rep.valid) {
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io.p_rep.ready := Bool(true)
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if(conf.ln.nTiles > 1) p_rep_count := p_rep_count - UFix(1)
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when(p_rep_count === UFix(1)) {
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state := s_mem
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}
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p_rep_data_needs_write := co.messageHasData(io.p_rep.bits.payload)
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}
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}
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is(s_mem) {
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when (p_rep_data_needs_write) {
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doMemReqWrite(io.mem_req_cmd,
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io.mem_req_data,
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io.mem_req_lock,
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io.p_rep_data,
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p_rep_data_needs_write,
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p_w_mem_cmd_sent,
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io.p_rep_data_dep.ready,
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io.p_rep_data_dep.valid && (io.p_rep_data_dep.bits.global_xact_id === UFix(id)))
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} . elsewhen(x_init_data_needs_write) {
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doMemReqWrite(io.mem_req_cmd,
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io.mem_req_data,
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io.mem_req_lock,
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io.x_init_data,
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x_init_data_needs_write,
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x_w_mem_cmd_sent,
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io.x_init_data_dep.ready,
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io.x_init_data_dep.valid && (io.x_init_data_dep.bits.global_xact_id === UFix(id)))
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} . elsewhen (x_needs_read) {
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doMemReqRead(io.mem_req_cmd, x_needs_read)
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} . otherwise {
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state := Mux(co.needsAckReply(xact.x_type, UFix(0)), s_ack,
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Mux(all_x_reps_require_acks, s_busy, s_idle))
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}
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}
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is(s_ack) {
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io.x_rep.valid := Bool(true)
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when(io.x_rep.ready) { state := Mux(all_x_reps_require_acks, s_busy, s_idle) }
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}
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is(s_busy) { // Nothing left to do but wait for transaction to complete
|
||||
when (io.free) {
|
||||
state := s_idle
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
def doMemReqWrite[T <: Data](req_cmd: FIFOIO[MemReqCmd], req_data: FIFOIO[MemData], lock: Bool, data: FIFOIO[LogicalNetworkIO[T]], trigger: Bool, cmd_sent: Bool, pop_dep: Bool, at_front_of_dep_queue: Bool) {
|
||||
req_cmd.bits.rw := Bool(true)
|
||||
req_data.bits := data.bits.payload
|
||||
when(req_cmd.ready && req_cmd.valid) {
|
||||
cmd_sent := Bool(true)
|
||||
}
|
||||
when (at_front_of_dep_queue) {
|
||||
req_cmd.valid := !cmd_sent && req_data.ready && data.valid
|
||||
lock := data.valid || cmd_sent
|
||||
when (req_cmd.ready || cmd_sent) {
|
||||
req_data.valid := data.valid
|
||||
when(req_data.ready) {
|
||||
data.ready:= Bool(true)
|
||||
when (data.valid) {
|
||||
mem_cnt := mem_cnt_next
|
||||
when(mem_cnt === UFix(REFILL_CYCLES-1)) {
|
||||
pop_dep := Bool(true)
|
||||
trigger := Bool(false)
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
def doMemReqRead(req_cmd: FIFOIO[MemReqCmd], trigger: Bool) {
|
||||
req_cmd.valid := Bool(true)
|
||||
req_cmd.bits.rw := Bool(false)
|
||||
when(req_cmd.ready) {
|
||||
trigger := Bool(false)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user