Andrew Waterman
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a0cb711451
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Start adding RoCC
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2013-09-14 15:31:50 -07:00 |
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Andrew Waterman
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d053bdc89f
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Remove Hwacha from Rocket
Soon it will use the coprocessor interface.
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2013-09-12 22:34:38 -07:00 |
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Andrew Waterman
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243c4ae342
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sync up rocket with new isa
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2013-09-12 03:44:38 -07:00 |
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Andrew Waterman
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67f80ba4b2
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Stall div/mul writeback until WB slot is free
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2013-08-24 14:44:17 -07:00 |
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Andrew Waterman
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52e31f3298
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Bypass scoreboard updates
This reduces div/mul/D$ miss latency by 1 cycle.
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2013-08-24 14:44:04 -07:00 |
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Andrew Waterman
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d4a0db4575
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Reflect ISA changes
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2013-08-24 14:43:55 -07:00 |
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Henry Cook
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3a266cbbfa
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final Reg changes
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2013-08-15 15:28:15 -07:00 |
|
Henry Cook
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1a9e43aa11
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initial attempt at upgrade
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2013-08-12 10:39:11 -07:00 |
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Henry Cook
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4eaab214d2
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Fold uncore constants into TileLinkConfiguration, update coherence API
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2013-08-02 16:29:51 -07:00 |
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Henry Cook
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9abdf4e154
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Make compatible with scala 2.10. List.sort deprecated. Refactor constants into package object.
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2013-07-23 20:27:58 -07:00 |
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Andrew Waterman
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95c5147dc5
|
Add RISC-V instruction disassembler
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2013-06-13 10:31:04 -07:00 |
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Andrew Waterman
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50ccc20bf3
|
replace RDNPC with AUIPC
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2013-04-22 04:20:15 -07:00 |
|
Andrew Waterman
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8cbdeb2abf
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add LR/SC support
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2013-04-04 17:07:09 -07:00 |
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Andrew Waterman
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8b439ef20d
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only support setpcr/clearpcr of SR
the full PCR RMW support was wasted area/power
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2013-04-04 17:07:08 -07:00 |
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Henry Cook
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6d2541aced
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nTiles -> nClients in LogicalNetworkConfig
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2013-03-20 14:12:36 -07:00 |
|
Henry Cook
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e1225c5114
|
standardize IO naming convention
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2013-01-07 13:41:36 -08:00 |
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Andrew Waterman
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78868f6075
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add config option to trade mul/div area for speed
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2013-01-06 03:47:17 -08:00 |
|
Andrew Waterman
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05f19b21d0
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merge multiplier and divider
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2012-12-12 02:22:47 -08:00 |
|
Andrew Waterman
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4608660f6e
|
torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
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2012-12-04 05:57:53 -08:00 |
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Andrew Waterman
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9c857b83f0
|
refactor PCR file
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2012-11-27 01:28:06 -08:00 |
|
Andrew Waterman
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352bb464b5
|
clock gate X/M and M/W store data registers
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2012-11-26 20:33:41 -08:00 |
|
Andrew Waterman
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de2f28193a
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get rid of more global constants
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2012-11-25 04:24:25 -08:00 |
|
Andrew Waterman
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c036cdc1ea
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add option for 2-cycle load-use delay
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2012-11-24 22:01:08 -08:00 |
|
Andrew Waterman
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72f94d1141
|
fix virtual address sign extension detection
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2012-11-20 04:06:57 -08:00 |
|
Andrew Waterman
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29bc361d6c
|
remove global constants; disentangle hwacha a bit
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2012-11-17 17:24:08 -08:00 |
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Andrew Waterman
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5a7777fe4d
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clock gate integer datapath more aggressively
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2012-11-17 06:48:44 -08:00 |
|
Andrew Waterman
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8dce89703a
|
new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
|
2012-11-16 02:39:33 -08:00 |
|
Yunsup Lee
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8764fe786a
|
refactored vector tlb
|
2012-11-06 23:53:52 -08:00 |
|
Andrew Waterman
|
4d1ca8ba3a
|
remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
|
2012-11-06 08:13:44 -08:00 |
|
Andrew Waterman
|
c5b93798fb
|
factor out more global constants
|
2012-11-05 23:52:32 -08:00 |
|
Andrew Waterman
|
5b20ed71be
|
move rd=0 check into bypass logic
before, the check was in the write enable logic, but moving it obviated
an awkward corner case for mtpcr with rd=0.
|
2012-11-05 01:30:57 -08:00 |
|
Andrew Waterman
|
7380c9fe60
|
aggressively clock gate int and fp datapaths
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2012-11-04 16:40:14 -08:00 |
|
Andrew Waterman
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5773cbb68a
|
rejigger htif to use UncoreConfiguration
|
2012-10-18 17:26:03 -07:00 |
|
Henry Cook
|
88ac5af181
|
Merged consts-as-traits
|
2012-10-16 16:32:35 -07:00 |
|
Andrew Waterman
|
197154c485
|
use BTB for JALR
|
2012-10-16 02:24:37 -07:00 |
|
Andrew Waterman
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661f8e635b
|
merge I$, ITLB, BTB into Frontend
|
2012-10-16 02:24:37 -07:00 |
|
Andrew Waterman
|
27ddff1adb
|
simplify and improve multiplier
|
2012-10-16 02:24:37 -07:00 |
|
Henry Cook
|
8970b635b2
|
improvements to implicit RocketConfiguration parameter
|
2012-10-15 16:29:49 -07:00 |
|
Henry Cook
|
9025d0610c
|
first pass at configuration object passed as implicit parameter
|
2012-10-07 22:37:29 -07:00 |
|
Henry Cook
|
dfdfddebe8
|
constants as traits
|
2012-10-07 22:20:03 -07:00 |
|
Huy Vo
|
0a97d6ab4d
|
type casting
|
2012-07-18 13:03:35 -07:00 |
|
Andrew Waterman
|
4e44ed7400
|
allow back pressure on IPI requests
|
2012-07-17 22:55:40 -07:00 |
|
Huy Vo
|
fd95159837
|
INPUT/OUTPUT orderring swapped
|
2012-07-12 18:16:57 -07:00 |
|
Huy Vo
|
7408c9ab69
|
removing wires
|
2012-05-24 10:42:39 -07:00 |
|
Henry Cook
|
622a801bb1
|
Refactored cpu/cache interface to use nested bundles
|
2012-05-02 11:54:28 -07:00 |
|
Andrew Waterman
|
7f254d9670
|
refine FP bugfixes
|
2012-04-01 14:52:33 -07:00 |
|
Huy Vo
|
c7c35322c2
|
two bug fixes to fpu
|
2012-03-31 22:23:51 -07:00 |
|
Yunsup Lee
|
a70f0414fa
|
fix a workaroundable bug
|
2012-03-26 20:51:54 -07:00 |
|
Andrew Waterman
|
86d56ff67b
|
refactor cpu/i$/d$ into Tile (rather than Top)
|
2012-03-24 16:57:28 -07:00 |
|
Andrew Waterman
|
54fa6f660d
|
new supervisor mode
|
2012-03-24 13:03:31 -07:00 |
|