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Commit Graph

5169 Commits

Author SHA1 Message Date
Andrew Waterman
130fa95ed6 expand HTIF's PCR register space 2012-07-27 14:52:39 -07:00
Andrew Waterman
7778802395 reduce number of outstanding transactions 2012-07-26 14:51:41 -07:00
Andrew Waterman
9c50621a19 remove chip-specific uncore gunk 2012-07-26 03:26:52 -07:00
Andrew Waterman
1ae3091261 memory system bug fixes 2012-07-26 00:05:21 -07:00
Andrew Waterman
1405718ca8 memory system bug fixes 2012-07-26 00:05:21 -07:00
Andrew Waterman
a5bea4364f memory system bug fixes 2012-07-26 00:05:21 -07:00
Yunsup Lee
3a2b305ddf change htif width to 16 2012-07-25 17:25:50 -07:00
Andrew Waterman
177dbdadd9 merge HTIF port and backup memory port 2012-07-25 00:18:02 -07:00
Yunsup Lee
309193dd07 change llc size 2012-07-24 14:10:29 -07:00
Yunsup Lee
7736405726 fix bug in coherence hub, respect xact_rep.ready 2012-07-23 20:56:55 -07:00
Yunsup Lee
d0e12c13f6 fix bug in coherence hub, respect xact_rep.ready 2012-07-23 20:56:55 -07:00
Yunsup Lee
6541cf22a4 fix bug in coherence hub, respect xact_rep.ready 2012-07-23 20:56:55 -07:00
Yunsup Lee
f4e3e72ad1 hoist HTIF_WIDTH out to consts 2012-07-23 17:30:04 -07:00
Andrew Waterman
a21c355114 fix htif split request/response 2012-07-23 17:15:16 -07:00
Andrew Waterman
df8aff0906 don't dequeue probe queue during reset 2012-07-22 21:05:52 -07:00
Andrew Waterman
c6ac836581 don't dequeue probe queue during reset 2012-07-22 21:05:52 -07:00
Andrew Waterman
938effc053 don't dequeue probe queue during reset 2012-07-22 21:05:52 -07:00
Yunsup Lee
379f021359 change ioHTIF interface between the tile/uncore boundary to cope with asynchrony 2012-07-22 18:26:02 -07:00
Yunsup Lee
c892950bf1 hoist out uncore as its own component 2012-07-22 17:48:17 -07:00
Huy Vo
0a97d6ab4d type casting 2012-07-18 13:03:35 -07:00
Andrew Waterman
d01e70c672 decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
2012-07-17 22:55:40 -07:00
Andrew Waterman
0258dfb23f decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
2012-07-17 22:55:40 -07:00
Andrew Waterman
f42c6afed2 decouple all interfaces between tile and top
also, add an "incoherent" bit to tilelink to indicate no probes needed
2012-07-17 22:55:40 -07:00
Andrew Waterman
4e44ed7400 allow back pressure on IPI requests 2012-07-17 22:55:40 -07:00
Yunsup Lee
f633a55722 fix dcache tag array size 2012-07-16 22:19:03 -07:00
Andrew Waterman
e496cd7584 use Mem to implement queues to speed things up 2012-07-13 21:48:05 -07:00
Huy Vo
a79747a062 INPUT/OUTPUT orderring swapped 2012-07-12 18:16:57 -07:00
Huy Vo
18bc14058b INPUT/OUTPUT orderring swapped 2012-07-12 18:16:57 -07:00
Huy Vo
fd95159837 INPUT/OUTPUT orderring swapped 2012-07-12 18:16:57 -07:00
Andrew Waterman
bac82762d3 use only one (wide) tag ram for set assoc. caches 2012-07-12 14:50:12 -07:00
Andrew Waterman
62a3ea4113 fix some LLC bugs 2012-07-11 17:56:39 -07:00
Andrew Waterman
0aa33bf909 fix some LLC bugs 2012-07-11 17:56:39 -07:00
Andrew Waterman
429fcbed8e fix some LLC bugs 2012-07-11 17:56:39 -07:00
Andrew Waterman
1ebfeeca8a add L2$
It still has performance bugs but no correctness bugs AFAIK.
2012-07-10 05:23:29 -07:00
Andrew Waterman
66cf690261 add L2$
It still has performance bugs but no correctness bugs AFAIK.
2012-07-10 05:23:29 -07:00
Andrew Waterman
f645fb4dd7 add L2$
It still has performance bugs but no correctness bugs AFAIK.
2012-07-10 05:23:29 -07:00
Andrew Waterman
5035374f36 update to new chisel 2012-07-08 17:59:41 -07:00
Andrew Waterman
39d198ecdc fix htif handling of large memory reads 2012-06-26 19:12:11 -07:00
Andrew Waterman
4e5f874266 update to new chisel/hwacha 2012-06-08 00:13:14 -07:00
Huy Vo
166b857055 ioDecoupled -> FIFOIO, ioPipe -> PipeIO 2012-06-06 18:22:56 -07:00
Huy Vo
0c6bade592 ioDecoupled -> FIFOIO, ioPipe -> PipeIO 2012-06-06 18:22:56 -07:00
Huy Vo
a99cebb483 ioDecoupled -> FIFOIO, ioPipe -> PipeIO 2012-06-06 18:22:56 -07:00
Huy Vo
9b3161920f moving util out into Chisel standard library 2012-06-06 12:51:26 -07:00
Huy Vo
f2942f79f9 moving util out into Chisel standard library 2012-06-06 12:51:26 -07:00
Huy Vo
04304fe788 moving util out into Chisel standard library 2012-06-06 12:51:26 -07:00
Huy Vo
c975c21e44 views removed 2012-06-06 12:51:26 -07:00
Andrew Waterman
943b6d0616 remove debug println 2012-06-06 02:48:48 -07:00
Andrew Waterman
7f6319047e update to new scala/chisel/Mem 2012-06-06 02:47:22 -07:00
Huy Vo
6f2f1ba21c removing wires 2012-05-24 10:42:39 -07:00
Huy Vo
0208e9f95e removing wires 2012-05-24 10:42:39 -07:00