riscv/rocket-chip
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Author SHA1 Message Date
Andrew Waterman 1ae7a9376c Fix unhandled LLC writeback hazard 2014-06-13 03:25:52 -07:00
Andrew Waterman 364a6de214 Use Mem instead of Vec[Reg] 2014-05-18 19:26:35 -07:00
Andrew Waterman 02dbd6b0aa Don't assign to your own inputs 2014-02-12 18:39:40 -08:00
Andrew Waterman 3e634aef1d Fix HTIF for cache line sizes other than 64 B 2014-01-22 18:20:36 -08:00
Andrew Waterman 4f1213cb8b Fix Scala integer overflow 2014-01-13 21:45:14 -08:00
Andrew Waterman acc0d2b06c Only use LSBs for HTIF control regs 
For now, at least...
 2013-11-25 04:34:16 -08:00
Andrew Waterman 7b019cb0da rmeove aborts 2013-03-19 15:30:23 -07:00
Andrew Waterman aae7a67781 fix llc refill/writeback bugs 2012-12-06 02:07:03 -08:00
Andrew Waterman 50e9d952e8 don't initiate llc refill until writeback drains 2012-12-04 06:57:53 -08:00
Andrew Waterman 8103676b37 reduce physical address space to 4GB 2012-11-26 20:54:56 -08:00
Andrew Waterman 56f9b9721d treat prefetches as read requests 2012-11-20 05:38:49 -08:00
Andrew Waterman 3e6dc35809 issue self-probes for uncached read transactions 
this facilitates I$ coherence.  but it seems like a hack and perhaps
the mechanism should be rethought.
 2012-11-16 02:37:56 -08:00
Andrew Waterman 2aecb0024f UncoreConfiguration now contains coherence policy 2012-10-18 16:57:28 -07:00
Andrew Waterman ffda0e41a9 parameterize width of MemSerdes/MemDesser 2012-10-18 16:56:36 -07:00
Andrew Waterman 3973aef938 handle structural hazard on LLC tags 2012-10-09 18:04:55 -07:00
Andrew Waterman 17dc2075dd fix some LLC control bugs 2012-08-06 17:10:04 -07:00
Andrew Waterman 115c25c34b fix some LLC control bugs 2012-08-06 17:10:04 -07:00
Andrew Waterman 875f3622af fix deadlock in coherence hub 2012-08-03 19:00:03 -07:00
Andrew Waterman 962423d2d1 fix deadlock in coherence hub 2012-08-03 19:00:03 -07:00
Andrew Waterman e346f21725 fix control bug in LLC 
structural hazard on tag ram caused deadlock
 2012-08-03 18:59:37 -07:00
Andrew Waterman 92b7504c9a fix control bug in LLC 
structural hazard on tag ram caused deadlock
 2012-08-03 18:59:37 -07:00
Andrew Waterman 7a75334bb9 pipeline LLC further 2012-07-31 17:45:14 -07:00
Andrew Waterman 7b9cfd0b90 pipeline LLC further 2012-07-31 17:45:14 -07:00
Andrew Waterman 8db233c9b7 further pipeline the LLC 2012-07-30 20:12:11 -07:00
Andrew Waterman 85dc34df80 further pipeline the LLC 2012-07-30 20:12:11 -07:00
Andrew Waterman 1ae3091261 memory system bug fixes 2012-07-26 00:05:21 -07:00
Andrew Waterman 1405718ca8 memory system bug fixes 2012-07-26 00:05:21 -07:00
Andrew Waterman df8aff0906 don't dequeue probe queue during reset 2012-07-22 21:05:52 -07:00
Andrew Waterman c6ac836581 don't dequeue probe queue during reset 2012-07-22 21:05:52 -07:00
Andrew Waterman d01e70c672 decouple all interfaces between tile and top 
also, add an "incoherent" bit to tilelink to indicate no probes needed
 2012-07-17 22:55:40 -07:00
Andrew Waterman 0258dfb23f decouple all interfaces between tile and top 
also, add an "incoherent" bit to tilelink to indicate no probes needed
 2012-07-17 22:55:40 -07:00
Andrew Waterman f804c57bb0 reduce HTIF clock divider for now 2012-05-03 04:21:11 -07:00
Andrew Waterman 98a5d682a5 coherence mostly works now 2012-04-10 02:22:45 -07:00
Andrew Waterman 2a7d2888a7 coherence mostly works now 2012-04-10 02:22:45 -07:00
Andrew Waterman 73d8d42515 fix coherence bug with multiple probe replies 2012-04-09 21:40:35 -07:00
Andrew Waterman 257747a3a1 no dessert tonight :( 2012-03-26 23:50:09 -07:00
Andrew Waterman 25fe46dc18 remove bug from dessert 2012-03-26 14:18:57 -07:00
Andrew Waterman 4e6302fedc add dessert 2012-03-25 23:03:20 -07:00
Andrew Waterman 5a00143035 loop host.in to host.out during reset 2012-03-25 21:45:10 -07:00
Andrew Waterman a7ebea13fc add mem serdes unit 2012-03-25 17:03:58 -07:00
Andrew Waterman e38114e4b0 fix coherence bug 
popping wrong store dependence queue
 2012-03-16 01:24:07 -07:00
Andrew Waterman 3129040bda use divided clk for htif. UDPATE YOUR FESVR 
by default, we now load programs via a backdoor, because otherwise
it takes too long to simulate.
 2012-03-15 18:36:51 -07:00
Andrew Waterman 77c405ffa1 use broadcast hub and coherent HTIF 2012-03-14 16:44:35 -07:00
Andrew Waterman 53cd543d3f fix minor coherence bugs 2012-03-13 19:10:54 -07:00
Andrew Waterman 53d69d3006 parameterize broadcast hub by # of tiles 2012-03-13 17:12:01 -07:00
Andrew Waterman 1258f31825 add probe unit 2012-03-13 16:43:51 -07:00
Andrew Waterman d777f1cb24 fix null hub store ack bug 2012-03-10 15:19:12 -08:00
Andrew Waterman 2607153b67 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-09 02:08:55 -08:00
Andrew Waterman 3a72ace057 Merge branch 'master' of github.com:ucb-bar/riscv-rocket 2012-03-09 02:08:55 -08:00
Andrew Waterman df6ac34821 coherence hub fixes 2012-03-07 21:03:44 -08:00
Andrew Waterman 7929600874 change D$ to use FourStateCoherence protocol 
instead of ThreeStateIncoherence.
 2012-03-07 01:26:35 -08:00
Andrew Waterman 012b991ffe implement transaction finish messages 2012-03-06 15:48:08 -08:00
Andrew Waterman 1024a460f2 support memory transaction aborts 2012-03-06 00:35:02 -08:00
Andrew Waterman 6ad7aa5cdc flip direction of ioPipe to match ioDecoupled 2012-03-02 16:18:32 -08:00
Andrew Waterman 4c3f7a36ce clean up D$ store data unit 2012-03-01 19:20:00 -08:00
Andrew Waterman 8b519e7ea8 replace tile memory interface with ioTileLink 
work in progress towards coherent HTIF. for now, requests
are incoherently passed through a null coherence hub.
 2012-02-29 03:10:47 -08:00
Andrew Waterman eec369a1c7 separate memory request command and data 
also, merge some VLSI/C++ test harness functionality
 2012-02-28 19:06:23 -08:00
Andrew Waterman 7d331858e2 replace ioDCache with ioMem 2012-02-27 18:36:09 -08:00
Andrew Waterman 71c8d3fd41 reorganize directory structure 2012-02-08 15:13:08 -08:00