riscv/rocket-chip
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clean up D$ store data unit

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This commit is contained in:
Andrew Waterman 2012-03-01 18:49:00 -08:00
parent de73eef409
commit 4c3f7a36ce
1 changed files with 5 additions and 2 deletions
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7
uncore/coherence.scala
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@ -90,8 +90,8 @@ class ioTileLink extends Bundle {
val xact_finish = (new ioDecoupled) { new TransactionFinish() }.flip
}
trait CoherencePolicy {
def cpuCmdToRW( cmd: Bits): (Bool, Bool) = {
object cpuCmdToRW {
def apply(cmd: Bits): (Bool, Bool) = {
val store = (cmd === M_XWR)
val load = (cmd === M_XRD)
val amo = cmd(3).toBool
@ -101,6 +101,9 @@ trait CoherencePolicy {
}
}
trait CoherencePolicy {
}
trait ThreeStateIncoherence extends CoherencePolicy {
val tileInvalid :: tileClean :: tileDirty :: Nil = Enum(3){ UFix() }