loop host.in to host.out during reset
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@ -28,7 +28,7 @@ class slowIO[T <: Data](divisor: Int, hold_cycles: Int)(data: => T) extends Comp
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val out_slow_bits = Reg() { data }
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val fromhost_q = new queue(1)(data)
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fromhost_q.io.enq.valid := in_en && io.in_slow.valid && in_slow_rdy
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fromhost_q.io.enq.valid := in_en && (io.in_slow.valid && in_slow_rdy || reset)
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fromhost_q.io.enq.bits := io.in_slow.bits
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fromhost_q.io.deq <> io.in_fast
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@ -39,7 +39,7 @@ class slowIO[T <: Data](divisor: Int, hold_cycles: Int)(data: => T) extends Comp
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when (out_en) {
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in_slow_rdy := fromhost_q.io.enq.ready
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out_slow_val := tohost_q.io.deq.valid
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out_slow_bits := tohost_q.io.deq.bits
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out_slow_bits := Mux(reset, fromhost_q.io.deq.bits, tohost_q.io.deq.bits)
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}
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io.in_slow.ready := in_slow_rdy
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