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Commit Graph

4565 Commits

Author SHA1 Message Date
Henry Cook
6b00e7ff74 New TileLink bundle names 2013-01-21 17:18:23 -08:00
Henry Cook
c211d74e95 New TileLink names 2013-01-21 17:17:26 -08:00
Henry Cook
72bba81a76 now using single-ported coherence master 2013-01-16 23:58:24 -08:00
Henry Cook
fb2644760f single-ported coherence master 2013-01-16 23:57:35 -08:00
Henry Cook
e33648532b Refactored packet headers/payloads 2013-01-15 15:57:06 -08:00
Henry Cook
f7c0152409 Refactored packet headers/payloads 2013-01-15 15:52:47 -08:00
Henry Cook
a2fa3fd04d Refactored packet headers/payloads 2013-01-15 15:50:37 -08:00
Henry Cook
a922b60152 Merge branch 'master' of github.com:ucb-bar/reference-chip into network-refactor 2013-01-07 14:23:49 -08:00
Henry Cook
f2cef8d8d2 new IO names, set val/rdy low for unused network inputs, add src/dst setting for tiles, incoherent sig out of tilelink, bump chisel/rocket/uncore 2013-01-07 14:19:55 -08:00
Henry Cook
f836bd93e1 Bugfix in crossbar ready sigs, added adapter for old hub, removed incoherent sig from tilelink 2013-01-07 14:01:39 -08:00
Henry Cook
418e3fdf50 Bugfix in crossbar ready sigs, added adapter for old hub, removed incoherent sig from tilelink 2013-01-07 13:57:48 -08:00
Henry Cook
e1225c5114 standardize IO naming convention 2013-01-07 13:41:36 -08:00
Henry Cook
261e14f831 Refactored uncore conf 2013-01-07 13:41:36 -08:00
Andrew Waterman
bbd010750f add missing #include 2013-01-06 04:53:40 -08:00
Andrew Waterman
fd727bf8aa add some of the zedboard fpga infrastructure
you can elaborate the RTL in fpga/build/vcs-sim-rtl, but there's no harness
for VCS simulation yet.
2013-01-06 03:58:10 -08:00
Andrew Waterman
03df2c3766 update .gitignores 2013-01-06 03:58:10 -08:00
Andrew Waterman
78868f6075 add config option to trade mul/div area for speed 2013-01-06 03:47:17 -08:00
Andrew Waterman
ce9f4881d2 remove broken multiplier early out 2013-01-06 03:47:00 -08:00
Henry Cook
d0805359a5 Refactored uncore conf 2012-12-13 11:46:29 -08:00
Henry Cook
400d48e3de Refactored uncore conf 2012-12-13 11:39:14 -08:00
Henry Cook
1d7f1a8182 Removed dummy tile instances 2012-12-12 16:44:03 -08:00
Henry Cook
0e73cc8c12 Removed dummy tile instances 2012-12-12 16:41:21 -08:00
Henry Cook
177909c955 Initial version of phys/log network compiles 2012-12-12 11:15:10 -08:00
Henry Cook
6d61baa6cd Initial version of phys/log network compiles 2012-12-12 11:08:50 -08:00
Henry Cook
f359518e52 wip: new network classes 2012-12-12 11:08:50 -08:00
Andrew Waterman
05f19b21d0 merge multiplier and divider 2012-12-12 02:22:47 -08:00
Andrew Waterman
c921fc34a9 merge ALU left and right shifters 2012-12-12 02:22:34 -08:00
Henry Cook
be4e5b8327 Initial version of phys/log network compiles 2012-12-12 00:06:14 -08:00
Henry Cook
8d69f9b41c Initial version of phys/log network compiles 2012-12-12 00:05:28 -08:00
Andrew Waterman
f5c53ce35d add ecc support to d$ data rams
i haven't injected errors yet; it may well be incorrect.
2012-12-11 15:58:53 -08:00
Yunsup Lee
98c0ea9875 push rocket, tests, and vt-libs 2012-12-07 16:59:15 -08:00
Andrew Waterman
3f59e439ef fix d$ tag raw hazard 2012-12-07 15:14:20 -08:00
Henry Cook
12caa55dc7 wip: new network classes 2012-12-06 18:51:30 -08:00
Andrew Waterman
e9752f1d72 pipeline host pcr access 2012-12-06 14:22:07 -08:00
Andrew Waterman
10a6a42a4a make vlsi use dram model by default 2012-12-06 03:13:45 -08:00
Andrew Waterman
4dda38204f fix d$ reset bug 2012-12-06 03:13:22 -08:00
Andrew Waterman
290d3d226c fix AMO and store bypass bugs
thanks, torture tester
2012-12-06 02:07:52 -08:00
Andrew Waterman
aae7a67781 fix llc refill/writeback bugs 2012-12-06 02:07:03 -08:00
Andrew Waterman
d911e635d6 simplify c++ memory models; support +dramsim flag
works for both vlsi and emulator
2012-12-04 07:04:26 -08:00
Andrew Waterman
50e9d952e8 don't initiate llc refill until writeback drains 2012-12-04 06:57:53 -08:00
Andrew Waterman
4608660f6e torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
2012-12-04 05:57:53 -08:00
Andrew Waterman
5dfb388f03 update to newest rocket 2012-11-27 02:43:31 -08:00
Andrew Waterman
90cae54ac4 fix D$ read/write concurrency bug 2012-11-27 02:42:27 -08:00
Andrew Waterman
9c857b83f0 refactor PCR file 2012-11-27 01:28:06 -08:00
Andrew Waterman
ea7029484e update to latest rocket 2012-11-26 20:57:12 -08:00
Andrew Waterman
8103676b37 reduce physical address space to 4GB 2012-11-26 20:54:56 -08:00
Andrew Waterman
64674d4d39 clean up PTW and support PADDR_BITS < VADDR_BITS 2012-11-26 20:38:45 -08:00
Andrew Waterman
608f65e716 don't wastefully read 2x the bits from D$ RAMs 2012-11-26 20:34:30 -08:00
Andrew Waterman
352bb464b5 clock gate X/M and M/W store data registers 2012-11-26 20:33:41 -08:00
Andrew Waterman
8a6ff5f9aa fix D$ writeback bug
I swear I did this last week... perhaps I am finally losing it!
2012-11-25 19:46:48 -08:00