Howard Mao
3b0e9167fa
add AXI to AHB converter and more conformant HASTI RAM
2016-05-06 11:32:03 -07:00
Howard Mao
dfcb73b6c9
groundtest only needs to write to a single tohost
2016-05-03 20:21:13 -07:00
Howard Mao
4045a07eda
Remove need for separate riscv-tests for groundtest
2016-05-03 18:29:46 -07:00
Howard Mao
8f891437b5
fix CacheFillTest
2016-05-03 14:57:05 -07:00
Andrew Waterman
15f4af19cf
Remove HTIF CPU port
2016-05-03 13:55:59 -07:00
Howard Mao
487d0b356e
fixes to get groundtest working with priv-1.9 changes
2016-05-03 13:09:44 -07:00
Andrew Waterman
c7c8ae5468
Instantiate PRCI block
2016-05-02 18:08:33 -07:00
Andrew Waterman
6d1e82bddf
Remove mtohost/mfromhost/mipi CSRs; stub out Rocket CSR port
2016-05-02 15:21:55 -07:00
Andrew Waterman
c4d2d29e80
Stub out debug module, rather than leaving it floating
2016-04-30 22:37:39 -07:00
Andrew Waterman
46bbbba5e6
New address map
2016-04-30 20:59:36 -07:00
Andrew Waterman
d0aa4c722d
More WIP on new memory map
2016-04-28 16:15:31 -07:00
Andrew Waterman
1f211b37df
WIP on new memory map
2016-04-27 14:57:54 -07:00
Colin Schmidt
48170fd9aa
add default cases to configs that use CDEMatchError
...
this avoids filling in the stack trace every time
a config doesn't contain the parameter
2016-04-22 12:14:58 -07:00
Howard Mao
f7af908969
put memory into the address map and no longer use MMIOBase
2016-04-21 18:53:16 -07:00
Howard Mao
c5838dd9b3
Fix narrow read/write behavior for AXI converters and fix L2 bugs
...
Until recently, we were assuming that the data channel in AXI was always
right-justified. However, for narrow writes, the data must actually be
aligned within the byte lanes. This commit changes some of the
converters in order to fix this issue.
There was a bug in the L2 cache in which a merged get request was
causing the tracker to read the old data from the data array,
overwriting the updated data acquired from outer memory. Changed it so
that pending_reads is no longer set if the data in the buffer is already
valid.
There was a bug in the PortedTileLinkCrossbar. The new GrantFromSrc and
FinishToDst types used client_id for routing to managers. This caused
bits to get cut off, which meant the Finish messages could not be routed
correctly. Changed to use manager_id instead.
2016-04-12 15:39:15 -07:00
Andrew Waterman
b43a85e2e8
Make ExampleSmallConfig/DefaultRV32Config smaller
2016-04-01 18:18:08 -07:00
Andrew Waterman
6878e3265f
Default RowBits to TileLink width, not XLen
2016-04-01 18:18:08 -07:00
Henry Cook
35d02c5096
LRSC fix. RocketChipNetwork moved to uncore.
2016-04-01 18:09:00 -07:00
Howard Mao
4f06a5ff6b
add memtest config for testing memory channel mux
2016-03-31 18:41:56 -07:00
Howard Mao
5a74a9b1e7
switch memory interconnect from AXI to TileLink
2016-03-31 18:18:30 -07:00
Howard Mao
7c3b57b8fa
switch MMIO network to TileLink
2016-03-31 14:30:10 -07:00
Howard Mao
c081a36893
Revert "Bump chisel3 and firrtl, add support for firrtl $ delimiter"
...
This reverts commit 5378f79b50
.
2016-03-30 19:06:32 -07:00
Howard Mao
1e03408323
get rid of mt benchmark suite
2016-03-29 20:16:07 -07:00
Howard Mao
ad93e0226d
Changes to prepare for switch to TileLink interconnect
...
We are planning on switching to a TileLink interconnect throughout and
convert to AXI only on the very edge. Therefore, we need to get rid of
all the existing AXI masters other than the TileLink to AXI converter.
* Get rid of DMA engine for now
* Connect RTC to TileLink interconnect instead of AXI interconnect
2016-03-29 20:16:07 -07:00
jackkoenig
5378f79b50
Bump chisel3 and firrtl, add support for firrtl $ delimiter
2016-03-29 20:16:07 -07:00
Howard Mao
9b9c662952
fix w_last wire
2016-03-29 20:16:07 -07:00
Howard Mao
e1a03cc9ac
fix issue with partial writemasks
2016-03-29 20:16:07 -07:00
Andrew Waterman
6c48dc3471
Use more sensible knob values for SmallConfig
2016-03-25 14:18:24 -07:00
Palmer Dabbelt
cddfdf0929
Add CHISEL_VERSION make argument
...
This allows users to specify if they want to build RocketChip against
Chisel 2 or 3. Since Chisel 3 is now open source we can add these
submodule pointers directly to avoid a fork of upstream.
2016-03-24 12:00:13 -07:00
Palmer Dabbelt
d697559754
Correct the polarity of the non-backup-memory HTIF
...
This fails in FIRRTL because <> has polarity now.
2016-03-24 12:00:13 -07:00
Palmer Dabbelt
c989ec5813
Fix the SCR file for Chisel 3
2016-03-21 11:55:40 -07:00
Howard Mao
e90a9dfb2b
make taking max of multiple integers in config a bit easier
2016-03-16 14:35:08 -07:00
Eric Love
4fc2a14a63
Fix MIF bug that cuts off upper xact id bits
2016-03-16 13:50:30 -07:00
Andrew Waterman
9dc0cbdfa4
WIP on privileged spec v1.9
2016-03-14 18:03:33 -07:00
Andrew Waterman
f2ded2721d
Merge branch 'master' into add-rv32-support
2016-03-10 19:33:04 -08:00
Andrew Waterman
25091003af
Add RV32 test/configuration options
...
These won't actually work until further commits. Rocket RV32 support
is complete, but on the priv-1.9 branch.
2016-03-10 17:40:21 -08:00
Andrew Waterman
7a75a03123
tabs are evil
2016-03-10 14:18:56 -08:00
Howard Mao
3c9e63f5a5
don't make HTIF clock divider tied to backup memory
2016-03-09 14:58:20 -08:00
Howard Mao
5e145515e1
fix some Chisel assertions
2016-03-02 14:50:49 -08:00
Albert Magyar
a80b0e959d
Add support for per-way cache metadata
...
Adds a new cache parameter (SplitMetadata) and an associated knob.
Closes #62
2016-03-01 13:03:24 -08:00
John Wright
ba96ad2b38
Move N_CORES and MMIO_BASE to SCRFile instance in RocketChip
2016-02-27 16:24:45 -08:00
Palmer Dabbelt
a0f3189c74
Change MIF_DATA_BITS back to 64
...
It turns out the Chisel C++ backend can't emit correct initialization
code for a 128 bit wide NastiROM. Rather than trying to fix Chisel, I'm
just going to hack up the backup memory port Verilog harness a bit more
to make it work.
Note that the backup memory port Verilog already couldn't take arbitrary
parameters for MIF_*, so it's not like we're losing any flexibility
here.
2016-02-27 11:43:44 -08:00
Palmer Dabbelt
9ea8c4e781
Add an 8-channel backup memory port config
...
Now that the backup memory port works I want to test it.
2016-02-27 10:56:13 -08:00
Palmer Dabbelt
7319f430d0
Fix the backup memory port on multiple-channel configs
...
The backup memory port doesn't work on multi-channel configurations, it
just screws up the Nasti tag bits. This patch always instantiates a
single-channel backup memory port, which relies on the memory channel
selector to only enable a single memory channel when the backup memory
port is enabled. There are some assertions to make sure this happens,
as otherwise memory gets silently corrupted.
While this is a bit of a hack, the backup memory port will be going away
soon so I don't want to spend a whole lot of time fixing it. The
generated hardware is actually very similar: we used to elaborate a
Nasti arbiter inside the backup memory support, now there's one outside
of it instead.
2016-02-27 10:47:52 -08:00
Palmer Dabbelt
7c0c48fac4
Resurrect the backup memory port
...
We need this to work for our chip, and it's not been tested in a long
time in upstream -- it didn't even used to build since the Nasti
conversion. This makes a few changes:
* Rather than calling the backup memory port parameters MEM_*, it calls
them MIF_* (to match the MIT* paramater objects). A new name was
necessary because the Nasti stuff is now dumped as MEM_*, which has
similar names but incompatible values.
* p(MIFDataBits) was changed back to 128, as otherwise the backup
memory port doesn't work (it only send half a TileLink transaction).
64 also causes readmemh to bail out, but changing the elf2hex parameters
works around that.
* A configuration was added that enabled the backup memory port in the
tester. While this is kind of an awkward way to do it, I want to
make sure I can start testing this regularly and this makes it easy to
integrate.
2016-02-27 10:46:56 -08:00
Yunsup Lee
a2381d2faf
RoCC PTW refactoring
2016-02-25 17:26:42 -08:00
Colin Schmidt
ef4915bd2c
make the asm suites ordered by their insertion order
2016-02-24 19:49:35 -08:00
Colin Schmidt
ad81d95751
add run-asm-{p,pt,v}-tests targets for convenience
2016-02-24 19:49:35 -08:00
John Wright
b04cd545b6
pass base SCR address to SCRFile for address calculation
2016-02-24 15:32:46 -08:00
Howard Mao
8a877fa620
Add Matthew Naylor's trace generator and AXE scripts
2016-02-24 14:39:11 -08:00
Howard Mao
8c02cb09ca
some additions to Travis and fixes for Testing
2016-02-23 23:37:29 -08:00
Palmer Dabbelt
c263c636b3
Actually reference all the tests from RISCV
2016-02-23 16:05:27 -08:00
Palmer Dabbelt
bae4c0c0c9
Point Testing to $RISCV/... not $base_dir/...
...
This uses the compiled tests in RISCV, which match the rest of the toolchain.
2016-02-23 10:58:51 -08:00
Colin Schmidt
4ce603e548
Memtest configs should not have a hex file loaded
2016-02-22 12:49:26 -08:00
Colin Schmidt
0c575403af
only use a single asm test and 1 bmark for memtest
2016-02-22 09:36:53 -08:00
Howard Mao
5e4a02038c
move FPGA AXI to HTIF converter into Chisel module
2016-02-19 13:53:31 -08:00
Palmer Dabbelt
926efd0cab
Allow the number of memory channels to be picked at runtime
...
We're building a chip with 8 memory channels. Since this will require a
complicated test setup we want to also be able to bring up the chip with fewer
memory channels. This commit adds a SCR that controls the number of active
memory channels on a chip. Toggling this SCR will scramble memory and drop
Nasti messages, so it's only possible to change while the chip is booting.
By default this just adds a 1-bit SCR, which essentially no extra logic.
When multiple memory channel configurations are enabled at elaboration time, a
NastiMemoryInterconnect is generated for each channel configuration. The
number of outstanding misses is increased to coorespond to the maximum number
of banks per memory channel (added as a parameter), which I believe is
necessary to avoid deadlock in the memory system.
A configuration is added that supports 8 memory channels but has only 1 enabled
by default.
2016-02-17 15:23:30 -08:00
Palmer Dabbelt
db9de94588
Generate and use SCR address header files
...
This uses the new SCRFile changes to generate a header file containing a list
of all the SCRs in a core to remove the magic constant "63" (the HTIF clock
divider control register) and replace it with a generated number (which is
still 63).
2016-02-17 15:23:18 -08:00
Christopher Celio
c1b4d9372f
Revert "add new parameters for new SCR file"
...
This reverts commit 4dad5b8b32
.
The commit breaks the build.
2016-02-13 04:02:20 -08:00
Christopher Celio
6c6bbca92a
Revert "use singleton for global"
...
This reverts commit 4d0f941de3
.
The commit breaks the build.
2016-02-13 03:56:47 -08:00
John Wright
4d0f941de3
use singleton for global
2016-02-13 00:56:11 -08:00
John Wright
4dad5b8b32
add new parameters for new SCR file
2016-02-12 18:24:12 -08:00
Howard Mao
9fb2216548
get rid of unused external mmio port
2016-02-10 21:49:02 -08:00
Howard Mao
72a876bfba
add NASTI to TL converter
2016-02-10 11:12:39 -08:00
Palmer Dabbelt
b2ed35e8aa
Print a better error on missing config classes
...
Without this you don't actually see what config class you tried to use, which
makes it hard to grep around Makefiles to see why things are broken.
2016-02-05 09:59:02 -08:00
Palmer Dabbelt
8422aaf6fc
Add a "/" when targetDir doesn't have one
...
This isn't Chisel 3 specific, but that's what I happened to do in the Chisel 3
Driver wrapper.
2016-02-05 09:57:47 -08:00
Palmer Dabbelt
3bb0f11e6c
Chisel3 <> reverse fix
2016-02-05 09:56:42 -08:00
Howard Mao
06c3f9b655
Rocket Chip fixes in response to lowRISC team's comments
...
* DMA frontend-backend communication tunneled over TileLink/AXI
* Split MMIO and Mem requests in l1tol2net instead of in AXI interconnect
* Don't make NIOMSHRs configurable. Fixed at 1.
* Connect accelerator-internal CSRs into the CSR file
* Make mtvec register configurable and writeable
2016-02-02 13:14:52 -08:00
Howard Mao
33aa64212d
fix more Chisel3 deprecations
2016-01-14 15:06:30 -08:00
Howard Mao
c06884b78c
lowercase SMI to Smi
2016-01-11 17:44:10 -08:00
Howard Mao
806e40d19b
implement DMA streaming functionality
2016-01-07 19:26:15 -08:00
Howard Mao
8190bf6e18
implement DMA unit
2015-12-16 21:27:48 -08:00
Howard Mao
1a272677ca
more fixes to L2 cache
2015-12-16 21:06:39 -08:00
Howard Mao
560fdc19a8
add PLRU replacement option to L2 cache
2015-12-16 10:24:57 -08:00
Howard Mao
7ad9deeaee
Fix issues with request merging in L2 cache and add regression tests
...
In addition to the fix, there are several additions to the
RegressionTest module. The set of regressions is now parameterized and
split into ones for the cache and ones for the broadcast hub.
2015-12-15 23:02:15 -08:00
Howard Mao
0c91e00676
move GroundTest configs to a separate file
2015-12-06 03:01:05 -08:00
Howard Mao
4f5dabcda2
add SCR file to device tree
2015-12-05 00:28:58 -08:00
Howard Mao
f35b83d3ca
allow configuration of rocket ICache buffering
2015-12-02 17:18:39 -08:00
Howard Mao
cdc476a370
change Rocc parameterization
2015-12-01 17:56:09 -08:00
Andrew Waterman
e0d849fec5
Fix zscale testing
...
Use the following command in vsim:
make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
2015-12-01 17:31:48 -08:00
Howard Mao
c8c68e75bb
base NGenerators on NTiles, not the other way around
2015-12-01 15:26:09 -08:00
Howard Mao
40d68406d6
use xlen parameter for ALU
2015-11-30 18:04:44 -08:00
Howard Mao
23f0756978
implement support for multiple RoCC accelerators
2015-11-26 12:49:04 -08:00
Andrew Waterman
e25a020e60
Construct device tree ROM in MMIO region
...
Rebuild riscv-tools for this to work!
2015-11-25 21:23:37 -08:00
Howard Mao
ec6bfde9a3
fix WritebackUnit issue in uncore
2015-11-21 16:11:22 -08:00
Howard Mao
9d50f37289
fix unused set issue for multiple L2 cache banks
2015-11-20 23:26:28 -08:00
Howard Mao
ad3b7fd0e1
adjust CacheFillTest configuration
2015-11-19 10:52:14 -08:00
Howard Mao
4806f72b08
add CacheFillTest to check L2 conflict misses
2015-11-19 00:16:28 -08:00
Howard Mao
3514b6eb87
add some more useful configurations
2015-11-18 22:11:17 -08:00
Howard Mao
379d43d5f4
make MultiChannel routing more performant
2015-11-18 22:11:17 -08:00
Andrew Waterman
5195a5b891
Remove IPI network
...
This is now provided via MMIO.
2015-11-16 21:53:14 -08:00
Howard Mao
a1063bad54
fix issues with non-allocating put/get
2015-11-12 15:54:34 -08:00
Howard Mao
6ddf81090b
didn't mean to turn off GenerateCached in last commit
2015-11-11 17:39:08 -08:00
Howard Mao
11f0b3d8db
restore old L2 cache AcquireTransactor configuration
2015-11-11 17:10:58 -08:00
Howard Mao
31da692ccc
default to single tile in WithMemtest
2015-11-11 14:54:13 -08:00
Howard Mao
55581195eb
add groundtest submodule for simple memory testing
2015-11-11 14:33:02 -08:00
Howard Mao
149480411e
make sure ClientTileLinkEnqueuer uses the correct parameters
2015-11-10 16:09:19 -08:00
Howard Mao
51f128ec74
actually use backendBuffering in front of unwrapper/converter chain
2015-11-09 11:50:18 -08:00
Howard Mao
bbf14ddc01
use definitions in consts header whenever possible
2015-11-05 10:48:32 -08:00
Howard Mao
7b252d8f89
get rid of now-unnecessary bits in MIF tag
2015-11-05 10:48:32 -08:00
Sagar Karandikar
ee9195be26
rename NBANKS knob to NBANKS_PER_MEM_CHANNEL for clarity
2015-11-05 10:48:32 -08:00
Sagar Karandikar
354abf5e6b
fix NSets calculation
2015-11-05 10:48:32 -08:00
Howard Mao
dcef020ca0
get multichannel simulation working in emulator
2015-11-05 10:48:32 -08:00
Howard Mao
04d92dddbd
add back decoupled NASTI connection at edge of RocketChip
2015-11-05 10:48:32 -08:00
Yunsup Lee
51116e0674
add 2 and 4 memory channel configs
2015-11-05 10:48:32 -08:00
Yunsup Lee
0d245741bc
add multichannel NASTI support in Verilog testbench
2015-11-05 10:48:32 -08:00
Howard Mao
9dabcab9c2
Get rid of MemIO in Top and replace with AXI throughout
2015-11-05 10:48:32 -08:00
Howard Mao
eb62ff6a50
add queues between Nasti -> TL converter and Nasti interconnect
2015-10-26 14:15:25 -07:00
Howard Mao
f37938e4de
implement MultiChannel routing
2015-10-26 14:15:25 -07:00
Yunsup Lee
a175afae73
make ZscaleChip work with new parameters framework
2015-10-25 10:24:39 -07:00
Colin Schmidt
854feab08e
add knob and constraint dumping
2015-10-22 17:25:38 -07:00
Henry Cook
9769b2747c
now depend on external cde library rather than chisel.params (bump all submodules)
2015-10-21 18:24:16 -07:00
Howard Mao
c311c9938e
nitpicky declaration move
2015-10-20 21:10:54 -07:00
Henry Cook
62765e9609
L2 rowBits param bugfix
2015-10-20 18:57:19 -07:00
Henry Cook
3fc630405b
Vectorize RoCC and Tile memory interfaces (bump uncore, rocket, zscale)
2015-10-20 15:05:12 -07:00
Henry Cook
8c3370c2e3
L2 AMOALU bugfix and simpler TileLinkParameters (bump rocket, uncore, zscale)
2015-10-16 19:15:47 -07:00
Howard Mao
c4117eb9a2
make sure TL parameters change properly throughout
...
* Outermost TL parameters should have the width set to be the same as the
MIF data width.
* Broadcast Hub and Narrower, which use different sets of TL parameters
should use the proper set of parameters at each interface
2015-10-14 18:03:39 -07:00
Henry Cook
4270fd78a5
Merge branch 'param-refactor-tl'
2015-10-14 12:16:22 -07:00
Henry Cook
dd5052888d
refactor tilelink params, compiles but ExampleSmallConfig fails
2015-10-13 23:44:05 -07:00
Howard Mao
a44e054c77
add support for different TileLink and MIF data widths
2015-10-13 12:46:23 -07:00
Henry Cook
9d11b64c75
added HasAddrMapParameters and GlobalAddrMap
2015-10-06 18:24:08 -07:00
Henry Cook
1c489d75c1
inject params at top-level for MemDessert
2015-10-06 16:26:58 -07:00
Henry Cook
c4eadbda57
Removed all traces of params
2015-10-06 11:42:06 -07:00
Henry Cook
38ae2707a3
refactor MemIO to not use params
2015-10-06 11:41:48 -07:00
Henry Cook
3d10a89907
refactor NASTI to not use param; new AddrMap class
2015-10-06 11:41:47 -07:00
Andrew Waterman
79cdf6efc0
Make perf counters optional
2015-09-28 13:56:08 -07:00
Howard Mao
7b0167b92e
make sure SCR and PCR data width matches xLen
2015-09-25 12:13:22 -07:00
Howard Mao
0d763524ef
make sure conf address map scales with number of cores
2015-09-25 09:41:19 -07:00
Howard Mao
8d4d8680bf
replace NASTIMasterIO and NASTISlaveIO with NASTIIO
2015-09-24 16:59:13 -07:00
Howard Mao
56ecdff52d
Implement NASTI-based Mem/IO interconnect
2015-09-22 10:32:31 -07:00
Andrew Waterman
c6bcc832a1
Chisel3: Don't use Vec.fill for IOs
2015-09-20 13:43:56 -07:00
Christopher Celio
c9d89226fb
Generated *.d file of tests now kept in order
...
-Changed Set to LinkedHashSet in Testing.scala
2015-09-11 18:36:04 -07:00
Andrew Waterman
700910adff
Chisel3 compatibility fix for <>
2015-08-05 15:34:40 -07:00
Andrew Waterman
34b9a7fdc5
Various Chisel3 compatibility changes
2015-08-03 18:54:56 -07:00
Henry Cook
0c9a7817b6
Reduce outstanding mem accesses for FPGAConfig (to reduce MIFTagBits < 7)
2015-07-30 16:30:00 -07:00
Henry Cook
51c42083d0
Add new junctions repo as submodule (contains externally facing buses and peripherals).
...
Bump all submodules.
2015-07-29 18:15:45 -07:00
Henry Cook
d21ffa4dba
Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used
2015-07-28 00:24:07 -07:00
Yunsup Lee
efd6458a3d
add zscale programs
2015-07-27 19:06:06 -07:00
Henry Cook
bd4ff35a4b
Upgrade sbt to 0.13.8, simplify build.scala Tasks, generate tests from TestGenerator App, set addons with env variable ROCKETCHIP_ADDONS
2015-07-22 11:49:10 -07:00
Yunsup Lee
a99b1e3a01
append config name to generated Makefrag filename
2015-07-17 12:34:49 -07:00
Yunsup Lee
e7802825c3
add Zscale testing
2015-07-17 12:02:02 -07:00
Yunsup Lee
4c7c3f5bb2
add test generate for ZscaleTop
2015-07-14 16:26:28 -07:00
Henry Cook
76046c52fe
Cleanup testing rv64uf
2015-07-13 18:58:58 -07:00
Henry Cook
302cd3e638
Added BuildZscale param for use in Top and makefrag generation
2015-07-13 15:46:42 -07:00
Henry Cook
407d8e473e
first cut at parameter-based testing
2015-07-13 14:54:26 -07:00
Henry Cook
4e4015089d
rename Configs source
2015-07-09 15:04:11 -07:00
Yunsup Lee
09e29e8fe0
add zscale
...
only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
2015-07-07 20:38:47 -07:00
Yunsup Lee
e6a13cdeba
New machine-mode timer facility
...
Mirroring Andrew's commit to reference-chip
2015-07-07 17:26:07 -07:00
Henry Cook
4fbb0f80ff
Added some multicore/multibanks named ChiselConfigs
2015-07-06 18:21:06 -07:00
Henry Cook
d3ccec1044
Massive update containing several months of changes from the now-defunct private chip repo.
...
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
2015-07-02 14:43:30 -07:00
Yunsup Lee
702ddabe26
add ExampleSmallConfig for README
2014-10-07 02:07:59 -07:00
Yunsup Lee
e25d420155
Improve ChiselConfig composability; bump chisel
2014-10-06 13:43:40 -07:00
Yunsup Lee
73eac94a65
Added "findBy" function to allow grouping parameters by location (e.g. L1D vs L1I), rather than grouping by field (e.g. NSets vs NWays)
2014-10-06 13:40:35 -07:00
Henry Cook
122733b3a9
file name consistency
2014-10-06 13:37:38 -07:00
Henry Cook
0b5f23a209
Streamlined uncore for release
2014-10-06 13:37:15 -07:00
Adam Izraelevitz
15fb4730ec
Add BuildTile parameter for Tile
...
Conflicts:
rocket
2014-09-25 06:50:45 -07:00
Henry Cook
7398b00d93
dir supplied by function
2014-09-25 06:50:41 -07:00
Henry Cook
5a840c5520
support for multiple tilelink paramerterizations in same design
2014-09-25 06:50:30 -07:00
Donggyu Kim
eb384f6461
new RocketChipBackend implementation
2014-09-25 06:47:12 -07:00
Scott Beamer
f2ca887de3
better fpga configs
2014-09-25 06:47:03 -07:00
Donggyu Kim
4fe48f5a0a
bump chisel
2014-09-25 06:46:58 -07:00
Donggyu Kim
60d90f5230
recover collectNodesIntoComp in Backends.scala
2014-09-25 06:46:50 -07:00
Donggyu Kim
a53091b40f
remove collectNodesIntoComp from Backends.scala
2014-09-25 06:46:27 -07:00
Scott Beamer
f4e6cd75ab
turn off fpu for default fpga config.
...
a larger fpga can use defaultconfig
2014-09-25 06:46:16 -07:00
Yunsup Lee
09de2e2794
compute number of outstanding misses for DRAMSideLLCNull
2014-09-12 18:09:38 -07:00
Yunsup Lee
1cfd9f5a0e
add LICENSE
2014-09-12 10:15:04 -07:00
Yunsup Lee
c98afa1fea
turn off DRAMSideLLC
2014-09-11 22:10:25 -07:00
Yunsup Lee
b5a64487eb
turn off DRAMSideLLC
2014-09-11 22:07:44 -07:00
Yunsup Lee
02c08a156f
generate consts.vh from chisel source
2014-09-10 17:14:55 -07:00
Yunsup Lee
6b6bdd2b83
decommission Slave top-level module for fpga build
2014-09-08 00:23:15 -07:00
Yunsup Lee
ddfd3ce968
further generalize fpga/vlsi builds
2014-09-08 00:21:57 -07:00
Henry Cook
ae05125f29
Adjustements to top-level parameters and knobs for hwacha
2014-09-07 17:57:33 -07:00
Henry Cook
4126678c9d
Merge branch 'dse'
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Conflicts:
rocket
uncore
2014-09-06 06:59:14 -07:00
Henry Cook
82467313dd
merge in rocketchip changes from master
2014-09-02 13:51:57 -07:00
Yunsup Lee
7734285507
forgot to comment out hwacha
2014-09-01 09:01:36 -07:00
Yunsup Lee
c03c09ec31
update for rocket-chip release
2014-08-31 20:26:55 -07:00
Henry Cook
78ab83d224
refactor fpga top/config
2014-08-28 13:07:54 -07:00
Henry Cook
bf356b9cb4
Refactor to combine fpga and vlsi tops, part 1
2014-08-24 19:30:53 -07:00
Henry Cook
a41d55b643
Final parameter refactor.
2014-08-23 01:26:03 -07:00
Scott Beamer
63b62394d9
added l2 to fpga
...
with new chisel & uncore, it goes into brams
2014-08-20 15:41:07 -07:00
Henry Cook
1563c1bb36
Fixed cache params. Asm and bmark tests pass.
2014-08-12 15:00:54 -07:00
Henry Cook
7f07771600
Cache utility traits. Completely compiles, asm tests hang.
2014-08-11 18:37:10 -07:00
Henry Cook
1983260e6f
a few more fixes. some param lookups fail (here() in Alter blocks)
2014-08-10 23:08:21 -07:00
Henry Cook
63bd0b9d2a
Partial conversion to params. Compiles but does not elaborate. Rocket and uncore conversion complete. FPGA and VLSI config are identical. HwachaConfig and MemoryControllerConfig not yet removed.
2014-08-08 12:27:47 -07:00
Adam Izraelevitz
08d81d0892
First cut at using new chisel parameters for toplevel parameters and fpu
2014-08-01 18:09:37 -07:00
Henry Cook
434da22283
Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel)
2014-05-28 17:16:49 -07:00
Henry Cook
b0ccb88982
make outer cache type choice a top-level const
2014-05-28 14:46:07 -07:00
Henry Cook
ce056b4b89
client/master -> inner/outer
2014-04-29 16:50:30 -07:00
Henry Cook
224e286dd3
New uncore config objects. Backends get their own file. Simplify fpga uncore.
2014-04-26 19:46:11 -07:00
Henry Cook
3d4273954a
TileLinkIO.GrantAck -> TileLinkIO.Finish
2014-04-26 15:19:25 -07:00
Henry Cook
fbf6e44376
fix connection error in fpga uncore
2014-04-24 11:58:59 -07:00
Henry Cook
cfd6748318
patches to make FAME1/dram IOs compile with up-to-date chisel (bumped)
2014-04-21 17:26:33 -07:00
Henry Cook
2cb4dbae39
Refactored uncore constants and tilelink data
2014-04-10 13:19:50 -07:00
Henry Cook
5a5f69bfca
finished uncore constant/tilelink data refactor
2014-04-10 13:13:46 -07:00
Andrew Waterman
817517c663
Better branch prediction
2014-04-07 16:08:06 -07:00
Henry Cook
56f515c255
first steps in uncore constant/tilelink data refactor
2014-03-30 09:21:08 -07:00
Andrew Waterman
d055c0ebaf
Push rocket/hardfloat/chisel
2014-03-04 16:39:06 -08:00
Yunsup Lee
e20d50436a
committed in the wrong directory, meant to commit in the hwacha directory
2014-03-01 00:01:35 -08:00
Yunsup Lee
8c459df3b6
flush deck when xcpt occurs, fixes remaining p test bugs
2014-02-28 22:50:34 -08:00
Stephen Twigg
755293d785
Push hwacha (refactoring) and add line that when uncommented properly instantiates hwacha).
2014-02-14 10:12:09 -08:00
Andrew Waterman
11e69a73cd
Fix tests when !hwacha; disable hwacha by default
2014-02-06 03:08:33 -08:00
Stephen Twigg
8c96e27ca6
Merge branch 'master' into hwacha-port
...
Mostly Stable version that is passing tests
2014-02-04 17:20:28 -08:00
Henry Cook
382fa0ef27
cleanups supporting uncore hierarchy
2014-01-31 16:03:58 -08:00
Stephen Twigg
e7ee94bcc8
Merge branch 'master' into hwacha-port
2014-01-21 15:23:05 -08:00
Stephen Twigg
ee0c4ca291
Push chisel, rocket, hwacha, tools, tests to incorporate a bunch of new changes (ISA alterations)
2014-01-21 14:48:04 -08:00
Andrew Waterman
6f028b2d52
Increase BTB size; fix Rocket FPU bug
2014-01-17 03:53:08 -08:00
Andrew Waterman
a43cf9d688
Update to new privileged ISA
2013-11-25 04:45:06 -08:00
Stephen Twigg
e50c5180cd
Merge branch 'master' into hwacha
2013-11-14 16:03:55 -08:00
Yunsup Lee
1d6d4b4e96
move htif to uncore
2013-11-07 13:19:19 -08:00
Yunsup Lee
c810847761
hookup all memory ports
2013-11-05 17:12:25 -08:00
Stephen Twigg
7da65434ee
Initial commit for the hwacha reference-chip/rocket re-integration.
2013-10-30 20:44:02 -07:00
Stephen Twigg
36dfff5ee8
Adjust Verilog testbench to use new debug_stats_pcr signal that has been exported to the top level. It is the or-reduction of the stats pcr for each core. Push rocket (export stats pcr to top level). This scheme is cleaner than digging into the hierarchy.
2013-09-25 01:21:41 -07:00
Andrew Waterman
b7d7ced41b
Update to new ISA
2013-09-21 06:40:23 -07:00
Huy Vo
09247c0e0b
fix to sram init pins
2013-09-19 20:12:10 -07:00
Andrew Waterman
80003b3019
Support RoCC
2013-09-15 04:25:26 -07:00
Andrew Waterman
fbdbb01232
update to new isa; disable vector tests
2013-09-12 17:04:03 -07:00
Henry Cook
b42e140e05
NetworkIOs no longer use thunks
2013-09-10 16:23:52 -07:00
Stephen Twigg
6cde69e95d
Merge changes from master. This updates rocket more than it should so while the emulator builds, programs will not execute correctly due to ISA changes, etc.
2013-09-09 14:31:18 -07:00
Yunsup Lee
ba9bbc27df
apply same change to fpga top-level
2013-08-24 15:50:03 -07:00
Yunsup Lee
76cd90fc01
parameterize number of SCRs
2013-08-24 15:47:42 -07:00
Yunsup Lee
0884bc9789
fix DRAMSideLLCNull entries
2013-08-24 13:20:38 -07:00
Yunsup Lee
1e3ac0afa9
back to NTILES=1
2013-08-24 13:10:30 -07:00
Henry Cook
b06d33da2f
Canonicalized sbt, updated makefiles, cleaned up submodules, minor bugfixes
2013-08-19 19:54:41 -07:00
Henry Cook
85e5ce046f
pulled submodule commits, uncore sbt standardized
2013-08-15 17:07:13 -07:00
Henry Cook
6b20556661
Merge branch 'chisel-v2' of github.com:ucb-bar/reference-chip into chisel-v2
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Conflicts:
chisel
riscv-hwacha
riscv-rocket
uncore
2013-08-15 16:39:30 -07:00
Henry Cook
784e017bae
Final Reg standardization
2013-08-15 16:37:58 -07:00
Henry Cook
9b70ecf546
Reg standardization
2013-08-13 17:53:19 -07:00
Huy Vo
cc6631ae4d
reset -> _reset
2013-08-12 20:52:55 -07:00
Henry Cook
11e131af47
initial attempt at upgrade
2013-08-12 10:46:22 -07:00
Henry Cook
199e76fc77
Fold uncore constants into TileLinkConfiguration, update coherence API
2013-08-02 16:31:27 -07:00
Henry Cook
4d916b56e3
Bump scala to 2.10.2, sbt to 0.13-RC2, including new launcher. Upgrade reflection in network.scala to 2.10 lib. Constants now obtained from subproject package objects. Give network its own file.
2013-07-24 23:28:43 -07:00
Henry Cook
2796de01bf
new tilelink arbiter types, reduced release xact trackers
2013-07-09 15:41:27 -07:00
Henry Cook
896179cbb6
removed bad mt test
2013-06-14 00:14:18 -07:00
Henry Cook
c06cbf523b
Redo network to use PairedData crossbars when necessary. Hard-coded network types for each message type. Bump chisel, rocket, uncore.
2013-05-23 15:26:20 -07:00
Henry Cook
6a69d7d7b5
pass closure to generate bank addr
2013-05-23 14:58:19 -07:00
Andrew Waterman
d825c9d6e9
make fpga Makefile work with updated Makefrag
2013-05-02 05:09:45 -07:00
Andrew Waterman
cfa86dba4f
add FPGA test bench
...
The memory models now support back pressure on the response.
2013-05-02 04:59:32 -07:00
Andrew Waterman
50bd9a08a7
resynchronize fpga uncore
2013-05-01 01:12:47 -07:00
Yunsup Lee
93df795e48
change LLC leaf SRAM size
2013-04-22 11:06:50 -07:00
Huy Vo
2ac3fd5306
get rid of init_node
2013-04-20 01:36:32 -07:00
Huy Vo
0d87e3bacc
fixed init pin generation
2013-04-20 00:38:01 -07:00
Henry Cook
a01cdf95fd
tell physical networks carring cache lines to lock arbitration for REFILL_CYCLES pumps
2013-04-10 13:53:27 -07:00
Henry Cook
16ad8a7e9c
Fixes after merge
2013-03-25 19:14:38 -07:00
Andrew Waterman
8e926f8d79
remove aborts
2013-03-25 17:01:46 -07:00
Henry Cook
eec590c1bf
Added support for multiple L2 banks. Moved tile IO queueing.
2013-03-25 17:01:46 -07:00
Henry Cook
806f897fc4
nTiles -> nClients in LogicalNetworkConfig
2013-03-25 17:01:46 -07:00
Andrew Waterman
ce4c1aa566
remove aborts
2013-03-25 17:01:46 -07:00
Henry Cook
cf76665d09
writebacks on release network pass asm tests and bmarks
2013-03-25 17:01:46 -07:00
Henry Cook
a0dc8d52d6
using new network and l2 controller
2013-03-25 17:01:46 -07:00
Yunsup Lee
9efe71412f
add DRAMSideLLCNull
2013-03-19 00:43:34 -07:00