806e40d19b
implement DMA streaming functionality
2016-01-07 19:26:15 -08:00
8190bf6e18
implement DMA unit
2015-12-16 21:27:48 -08:00
1a272677ca
more fixes to L2 cache
2015-12-16 21:06:39 -08:00
560fdc19a8
add PLRU replacement option to L2 cache
2015-12-16 10:24:57 -08:00
7ad9deeaee
Fix issues with request merging in L2 cache and add regression tests
...
In addition to the fix, there are several additions to the
RegressionTest module. The set of regressions is now parameterized and
split into ones for the cache and ones for the broadcast hub.
2015-12-15 23:02:15 -08:00
0c91e00676
move GroundTest configs to a separate file
2015-12-06 03:01:05 -08:00
4f5dabcda2
add SCR file to device tree
2015-12-05 00:28:58 -08:00
f35b83d3ca
allow configuration of rocket ICache buffering
2015-12-02 17:18:39 -08:00
cdc476a370
change Rocc parameterization
2015-12-01 17:56:09 -08:00
e0d849fec5
Fix zscale testing
...
Use the following command in vsim:
make CONFIG=ZscaleConfig MODEL=ZscaleTop TB=ZscaleTestHarness run-asm-tests
2015-12-01 17:31:48 -08:00
c8c68e75bb
base NGenerators on NTiles, not the other way around
2015-12-01 15:26:09 -08:00
40d68406d6
use xlen parameter for ALU
2015-11-30 18:04:44 -08:00
23f0756978
implement support for multiple RoCC accelerators
2015-11-26 12:49:04 -08:00
e25a020e60
Construct device tree ROM in MMIO region
...
Rebuild riscv-tools for this to work!
2015-11-25 21:23:37 -08:00
ec6bfde9a3
fix WritebackUnit issue in uncore
2015-11-21 16:11:22 -08:00
9d50f37289
fix unused set issue for multiple L2 cache banks
2015-11-20 23:26:28 -08:00
ad3b7fd0e1
adjust CacheFillTest configuration
2015-11-19 10:52:14 -08:00
4806f72b08
add CacheFillTest to check L2 conflict misses
2015-11-19 00:16:28 -08:00
3514b6eb87
add some more useful configurations
2015-11-18 22:11:17 -08:00
379d43d5f4
make MultiChannel routing more performant
2015-11-18 22:11:17 -08:00
5195a5b891
Remove IPI network
...
This is now provided via MMIO.
2015-11-16 21:53:14 -08:00
a1063bad54
fix issues with non-allocating put/get
2015-11-12 15:54:34 -08:00
6ddf81090b
didn't mean to turn off GenerateCached in last commit
2015-11-11 17:39:08 -08:00
11f0b3d8db
restore old L2 cache AcquireTransactor configuration
2015-11-11 17:10:58 -08:00
31da692ccc
default to single tile in WithMemtest
2015-11-11 14:54:13 -08:00
55581195eb
add groundtest submodule for simple memory testing
2015-11-11 14:33:02 -08:00
149480411e
make sure ClientTileLinkEnqueuer uses the correct parameters
2015-11-10 16:09:19 -08:00
51f128ec74
actually use backendBuffering in front of unwrapper/converter chain
2015-11-09 11:50:18 -08:00
bbf14ddc01
use definitions in consts header whenever possible
2015-11-05 10:48:32 -08:00
7b252d8f89
get rid of now-unnecessary bits in MIF tag
2015-11-05 10:48:32 -08:00
ee9195be26
rename NBANKS knob to NBANKS_PER_MEM_CHANNEL for clarity
2015-11-05 10:48:32 -08:00
354abf5e6b
fix NSets calculation
2015-11-05 10:48:32 -08:00
dcef020ca0
get multichannel simulation working in emulator
2015-11-05 10:48:32 -08:00
04d92dddbd
add back decoupled NASTI connection at edge of RocketChip
2015-11-05 10:48:32 -08:00
51116e0674
add 2 and 4 memory channel configs
2015-11-05 10:48:32 -08:00
0d245741bc
add multichannel NASTI support in Verilog testbench
2015-11-05 10:48:32 -08:00
9dabcab9c2
Get rid of MemIO in Top and replace with AXI throughout
2015-11-05 10:48:32 -08:00
eb62ff6a50
add queues between Nasti -> TL converter and Nasti interconnect
2015-10-26 14:15:25 -07:00
f37938e4de
implement MultiChannel routing
2015-10-26 14:15:25 -07:00
a175afae73
make ZscaleChip work with new parameters framework
2015-10-25 10:24:39 -07:00
854feab08e
add knob and constraint dumping
2015-10-22 17:25:38 -07:00
9769b2747c
now depend on external cde library rather than chisel.params (bump all submodules)
2015-10-21 18:24:16 -07:00
c311c9938e
nitpicky declaration move
2015-10-20 21:10:54 -07:00
62765e9609
L2 rowBits param bugfix
2015-10-20 18:57:19 -07:00
3fc630405b
Vectorize RoCC and Tile memory interfaces (bump uncore, rocket, zscale)
2015-10-20 15:05:12 -07:00
8c3370c2e3
L2 AMOALU bugfix and simpler TileLinkParameters (bump rocket, uncore, zscale)
2015-10-16 19:15:47 -07:00
c4117eb9a2
make sure TL parameters change properly throughout
...
* Outermost TL parameters should have the width set to be the same as the
MIF data width.
* Broadcast Hub and Narrower, which use different sets of TL parameters
should use the proper set of parameters at each interface
2015-10-14 18:03:39 -07:00
4270fd78a5
Merge branch 'param-refactor-tl'
2015-10-14 12:16:22 -07:00
dd5052888d
refactor tilelink params, compiles but ExampleSmallConfig fails
2015-10-13 23:44:05 -07:00
a44e054c77
add support for different TileLink and MIF data widths
2015-10-13 12:46:23 -07:00
