riscv/rocket-chip
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Get rid of MemIO in Top and replace with AXI throughout

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This commit is contained in:
Howard Mao
2015-10-14 11:33:18 -07:00
parent 032bdd0601
commit 9dabcab9c2
10 changed files with 651 additions and 299 deletions
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28
src/main/scala/Configs.scala
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@ -40,20 +40,22 @@ class DefaultConfig extends Config (
case PPNBits => site(PAddrBits) - site(PgIdxBits)
case VAddrBits => site(VPNBits) + site(PgIdxBits)
case ASIdBits => 7
case MIFTagBits => Dump("MEM_TAG_BITS",
// Bits needed at the L2 agent
log2Up(site(NAcquireTransactors)+2) +
// Bits added by NASTI interconnect
log2Up(site(NMemoryChannels) * site(NBanksPerMemoryChannel) + 1) +
// Bits added by final arbiter (not needed if true multichannel memory)
log2Up(site(NMemoryChannels)))
case MIFDataBits => Dump("MEM_DATA_BITS", 128)
case MIFAddrBits => Dump("MEM_ADDR_BITS", site(PAddrBits) - site(CacheBlockOffsetBits))
case MIFTagBits => // Bits needed at the L2 agent
log2Up(site(NAcquireTransactors)+2) +
// Bits added by NASTI interconnect
log2Up(site(NMemoryChannels) * site(NBanksPerMemoryChannel) + 1) +
// Bits added by final arbiter (not needed if true multichannel memory)
log2Up(site(NMemoryChannels))
case MIFDataBits => 64
case MIFAddrBits => site(PAddrBits) - site(CacheBlockOffsetBits)
case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits)
case NastiKey => NastiParameters(
dataBits = site(MIFDataBits),
addrBits = site(PAddrBits),
idBits = site(MIFTagBits))
case NastiKey => {
Dump("MEM_STRB_BITS", site(MIFDataBits) / 8)
NastiParameters(
dataBits = Dump("MEM_DATA_BITS", site(MIFDataBits)),
addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
}
//Params used by all caches
case NSets => findBy(CacheName)
case NWays => findBy(CacheName)

16
src/main/scala/RocketChip.scala
View File

@ -68,7 +68,7 @@ class BasicTopIO(implicit val p: Parameters) extends ParameterizedBundle()(p)
}
class TopIO(implicit p: Parameters) extends BasicTopIO()(p) {
val mem = new MemIO
val mem = new NastiIO
}
class MultiChannelTopIO(implicit p: Parameters) extends BasicTopIO()(p) {
@ -96,15 +96,19 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
val temp = Module(new MultiChannelTop)
val arb = Module(new NastiArbiter(nMemChannels))
val conv = Module(new MemIONastiIOConverter(p(CacheBlockOffsetBits)))
arb.io.master <> temp.io.mem
conv.io.nasti <> arb.io.slave
io.mem.req_cmd <> Queue(conv.io.mem.req_cmd)
io.mem.req_data <> Queue(conv.io.mem.req_data, mifDataBeats)
conv.io.mem.resp <> Queue(io.mem.resp, mifDataBeats)
io.mem.ar <> Queue(arb.io.slave.ar)
io.mem.aw <> Queue(arb.io.slave.aw)
io.mem.w <> Queue(arb.io.slave.w)
arb.io.slave.r <> Queue(io.mem.r)
arb.io.slave.b <> Queue(io.mem.b)
io.mem_backup_ctrl <> temp.io.mem_backup_ctrl
io.host <> temp.io.host
// Memory cache type should be normal non-cacheable bufferable
io.mem.ar.bits.cache := UInt("b0011")
io.mem.aw.bits.cache := UInt("b0011")
// tie off the mmio port
val errslave = Module(new NastiErrorSlave)
errslave.io <> temp.io.mmio