Andrew Waterman
5195a5b891
Remove IPI network
...
This is now provided via MMIO.
2015-11-16 21:53:14 -08:00
Howard Mao
a1063bad54
fix issues with non-allocating put/get
2015-11-12 15:54:34 -08:00
Howard Mao
6ddf81090b
didn't mean to turn off GenerateCached in last commit
2015-11-11 17:39:08 -08:00
Howard Mao
11f0b3d8db
restore old L2 cache AcquireTransactor configuration
2015-11-11 17:10:58 -08:00
Howard Mao
31da692ccc
default to single tile in WithMemtest
2015-11-11 14:54:13 -08:00
Howard Mao
55581195eb
add groundtest submodule for simple memory testing
2015-11-11 14:33:02 -08:00
Howard Mao
149480411e
make sure ClientTileLinkEnqueuer uses the correct parameters
2015-11-10 16:09:19 -08:00
Howard Mao
51f128ec74
actually use backendBuffering in front of unwrapper/converter chain
2015-11-09 11:50:18 -08:00
Howard Mao
bbf14ddc01
use definitions in consts header whenever possible
2015-11-05 10:48:32 -08:00
Howard Mao
7b252d8f89
get rid of now-unnecessary bits in MIF tag
2015-11-05 10:48:32 -08:00
Sagar Karandikar
ee9195be26
rename NBANKS knob to NBANKS_PER_MEM_CHANNEL for clarity
2015-11-05 10:48:32 -08:00
Sagar Karandikar
354abf5e6b
fix NSets calculation
2015-11-05 10:48:32 -08:00
Howard Mao
dcef020ca0
get multichannel simulation working in emulator
2015-11-05 10:48:32 -08:00
Howard Mao
04d92dddbd
add back decoupled NASTI connection at edge of RocketChip
2015-11-05 10:48:32 -08:00
Yunsup Lee
51116e0674
add 2 and 4 memory channel configs
2015-11-05 10:48:32 -08:00
Yunsup Lee
0d245741bc
add multichannel NASTI support in Verilog testbench
2015-11-05 10:48:32 -08:00
Howard Mao
9dabcab9c2
Get rid of MemIO in Top and replace with AXI throughout
2015-11-05 10:48:32 -08:00
Howard Mao
eb62ff6a50
add queues between Nasti -> TL converter and Nasti interconnect
2015-10-26 14:15:25 -07:00
Howard Mao
f37938e4de
implement MultiChannel routing
2015-10-26 14:15:25 -07:00
Yunsup Lee
a175afae73
make ZscaleChip work with new parameters framework
2015-10-25 10:24:39 -07:00
Colin Schmidt
854feab08e
add knob and constraint dumping
2015-10-22 17:25:38 -07:00
Henry Cook
9769b2747c
now depend on external cde library rather than chisel.params (bump all submodules)
2015-10-21 18:24:16 -07:00
Howard Mao
c311c9938e
nitpicky declaration move
2015-10-20 21:10:54 -07:00
Henry Cook
62765e9609
L2 rowBits param bugfix
2015-10-20 18:57:19 -07:00
Henry Cook
3fc630405b
Vectorize RoCC and Tile memory interfaces (bump uncore, rocket, zscale)
2015-10-20 15:05:12 -07:00
Henry Cook
8c3370c2e3
L2 AMOALU bugfix and simpler TileLinkParameters (bump rocket, uncore, zscale)
2015-10-16 19:15:47 -07:00
Howard Mao
c4117eb9a2
make sure TL parameters change properly throughout
...
* Outermost TL parameters should have the width set to be the same as the
MIF data width.
* Broadcast Hub and Narrower, which use different sets of TL parameters
should use the proper set of parameters at each interface
2015-10-14 18:03:39 -07:00
Henry Cook
4270fd78a5
Merge branch 'param-refactor-tl'
2015-10-14 12:16:22 -07:00
Henry Cook
dd5052888d
refactor tilelink params, compiles but ExampleSmallConfig fails
2015-10-13 23:44:05 -07:00
Howard Mao
a44e054c77
add support for different TileLink and MIF data widths
2015-10-13 12:46:23 -07:00
Henry Cook
9d11b64c75
added HasAddrMapParameters and GlobalAddrMap
2015-10-06 18:24:08 -07:00
Henry Cook
1c489d75c1
inject params at top-level for MemDessert
2015-10-06 16:26:58 -07:00
Henry Cook
c4eadbda57
Removed all traces of params
2015-10-06 11:42:06 -07:00
Henry Cook
38ae2707a3
refactor MemIO to not use params
2015-10-06 11:41:48 -07:00
Henry Cook
3d10a89907
refactor NASTI to not use param; new AddrMap class
2015-10-06 11:41:47 -07:00
Andrew Waterman
79cdf6efc0
Make perf counters optional
2015-09-28 13:56:08 -07:00
Howard Mao
7b0167b92e
make sure SCR and PCR data width matches xLen
2015-09-25 12:13:22 -07:00
Howard Mao
0d763524ef
make sure conf address map scales with number of cores
2015-09-25 09:41:19 -07:00
Howard Mao
8d4d8680bf
replace NASTIMasterIO and NASTISlaveIO with NASTIIO
2015-09-24 16:59:13 -07:00
Howard Mao
56ecdff52d
Implement NASTI-based Mem/IO interconnect
2015-09-22 10:32:31 -07:00
Andrew Waterman
c6bcc832a1
Chisel3: Don't use Vec.fill for IOs
2015-09-20 13:43:56 -07:00
Christopher Celio
c9d89226fb
Generated *.d file of tests now kept in order
...
-Changed Set to LinkedHashSet in Testing.scala
2015-09-11 18:36:04 -07:00
Andrew Waterman
700910adff
Chisel3 compatibility fix for <>
2015-08-05 15:34:40 -07:00
Andrew Waterman
34b9a7fdc5
Various Chisel3 compatibility changes
2015-08-03 18:54:56 -07:00
Henry Cook
0c9a7817b6
Reduce outstanding mem accesses for FPGAConfig (to reduce MIFTagBits < 7)
2015-07-30 16:30:00 -07:00
Henry Cook
51c42083d0
Add new junctions repo as submodule (contains externally facing buses and peripherals).
...
Bump all submodules.
2015-07-29 18:15:45 -07:00
Henry Cook
d21ffa4dba
Streamline makefiles for more robust test dependency generation. Note: emulator/generated-src-debug no longer used
2015-07-28 00:24:07 -07:00
Yunsup Lee
efd6458a3d
add zscale programs
2015-07-27 19:06:06 -07:00
Henry Cook
bd4ff35a4b
Upgrade sbt to 0.13.8, simplify build.scala Tasks, generate tests from TestGenerator App, set addons with env variable ROCKETCHIP_ADDONS
2015-07-22 11:49:10 -07:00
Yunsup Lee
a99b1e3a01
append config name to generated Makefrag filename
2015-07-17 12:34:49 -07:00
Yunsup Lee
e7802825c3
add Zscale testing
2015-07-17 12:02:02 -07:00
Yunsup Lee
4c7c3f5bb2
add test generate for ZscaleTop
2015-07-14 16:26:28 -07:00
Henry Cook
76046c52fe
Cleanup testing rv64uf
2015-07-13 18:58:58 -07:00
Henry Cook
302cd3e638
Added BuildZscale param for use in Top and makefrag generation
2015-07-13 15:46:42 -07:00
Henry Cook
407d8e473e
first cut at parameter-based testing
2015-07-13 14:54:26 -07:00
Henry Cook
4e4015089d
rename Configs source
2015-07-09 15:04:11 -07:00
Yunsup Lee
09e29e8fe0
add zscale
...
only supports generating Verilog, which plugs into the fpga-spartan6 repository, for now
2015-07-07 20:38:47 -07:00
Yunsup Lee
e6a13cdeba
New machine-mode timer facility
...
Mirroring Andrew's commit to reference-chip
2015-07-07 17:26:07 -07:00
Henry Cook
4fbb0f80ff
Added some multicore/multibanks named ChiselConfigs
2015-07-06 18:21:06 -07:00
Henry Cook
d3ccec1044
Massive update containing several months of changes from the now-defunct private chip repo.
...
* Adds support for a L2 cache with directory bits for tracking L1 coherence (DefaultL2Config), and new metadata-based coherence API.
* Additional tests.
* New virtual memory implementation, priviliged architecture (1.7), custom CSRs, FDivSqrt unit
* Updated TileLink protocol, NASTI protocol SHIMs.
* Lays groundwork for multiple top-level memory channels, superscalar fetch.
* Bump all submodules.
2015-07-02 14:43:30 -07:00
Yunsup Lee
702ddabe26
add ExampleSmallConfig for README
2014-10-07 02:07:59 -07:00
Yunsup Lee
e25d420155
Improve ChiselConfig composability; bump chisel
2014-10-06 13:43:40 -07:00
Yunsup Lee
73eac94a65
Added "findBy" function to allow grouping parameters by location (e.g. L1D vs L1I), rather than grouping by field (e.g. NSets vs NWays)
2014-10-06 13:40:35 -07:00
Henry Cook
122733b3a9
file name consistency
2014-10-06 13:37:38 -07:00
Henry Cook
0b5f23a209
Streamlined uncore for release
2014-10-06 13:37:15 -07:00
Adam Izraelevitz
15fb4730ec
Add BuildTile parameter for Tile
...
Conflicts:
rocket
2014-09-25 06:50:45 -07:00
Henry Cook
7398b00d93
dir supplied by function
2014-09-25 06:50:41 -07:00
Henry Cook
5a840c5520
support for multiple tilelink paramerterizations in same design
2014-09-25 06:50:30 -07:00
Donggyu Kim
eb384f6461
new RocketChipBackend implementation
2014-09-25 06:47:12 -07:00
Scott Beamer
f2ca887de3
better fpga configs
2014-09-25 06:47:03 -07:00
Donggyu Kim
4fe48f5a0a
bump chisel
2014-09-25 06:46:58 -07:00
Donggyu Kim
60d90f5230
recover collectNodesIntoComp in Backends.scala
2014-09-25 06:46:50 -07:00
Donggyu Kim
a53091b40f
remove collectNodesIntoComp from Backends.scala
2014-09-25 06:46:27 -07:00
Scott Beamer
f4e6cd75ab
turn off fpu for default fpga config.
...
a larger fpga can use defaultconfig
2014-09-25 06:46:16 -07:00
Yunsup Lee
09de2e2794
compute number of outstanding misses for DRAMSideLLCNull
2014-09-12 18:09:38 -07:00
Yunsup Lee
1cfd9f5a0e
add LICENSE
2014-09-12 10:15:04 -07:00
Yunsup Lee
c98afa1fea
turn off DRAMSideLLC
2014-09-11 22:10:25 -07:00
Yunsup Lee
b5a64487eb
turn off DRAMSideLLC
2014-09-11 22:07:44 -07:00
Yunsup Lee
02c08a156f
generate consts.vh from chisel source
2014-09-10 17:14:55 -07:00
Yunsup Lee
6b6bdd2b83
decommission Slave top-level module for fpga build
2014-09-08 00:23:15 -07:00
Yunsup Lee
ddfd3ce968
further generalize fpga/vlsi builds
2014-09-08 00:21:57 -07:00
Henry Cook
ae05125f29
Adjustements to top-level parameters and knobs for hwacha
2014-09-07 17:57:33 -07:00
Henry Cook
4126678c9d
Merge branch 'dse'
...
Conflicts:
rocket
uncore
2014-09-06 06:59:14 -07:00
Henry Cook
82467313dd
merge in rocketchip changes from master
2014-09-02 13:51:57 -07:00
Yunsup Lee
7734285507
forgot to comment out hwacha
2014-09-01 09:01:36 -07:00
Yunsup Lee
c03c09ec31
update for rocket-chip release
2014-08-31 20:26:55 -07:00
Henry Cook
78ab83d224
refactor fpga top/config
2014-08-28 13:07:54 -07:00
Henry Cook
bf356b9cb4
Refactor to combine fpga and vlsi tops, part 1
2014-08-24 19:30:53 -07:00
Henry Cook
a41d55b643
Final parameter refactor.
2014-08-23 01:26:03 -07:00
Scott Beamer
63b62394d9
added l2 to fpga
...
with new chisel & uncore, it goes into brams
2014-08-20 15:41:07 -07:00
Henry Cook
1563c1bb36
Fixed cache params. Asm and bmark tests pass.
2014-08-12 15:00:54 -07:00
Henry Cook
7f07771600
Cache utility traits. Completely compiles, asm tests hang.
2014-08-11 18:37:10 -07:00
Henry Cook
1983260e6f
a few more fixes. some param lookups fail (here() in Alter blocks)
2014-08-10 23:08:21 -07:00
Henry Cook
63bd0b9d2a
Partial conversion to params. Compiles but does not elaborate. Rocket and uncore conversion complete. FPGA and VLSI config are identical. HwachaConfig and MemoryControllerConfig not yet removed.
2014-08-08 12:27:47 -07:00
Adam Izraelevitz
08d81d0892
First cut at using new chisel parameters for toplevel parameters and fpu
2014-08-01 18:09:37 -07:00
Henry Cook
434da22283
Refactored Metadata, expanded coherence API (bump rocket, uncore, chisel)
2014-05-28 17:16:49 -07:00
Henry Cook
b0ccb88982
make outer cache type choice a top-level const
2014-05-28 14:46:07 -07:00
Henry Cook
ce056b4b89
client/master -> inner/outer
2014-04-29 16:50:30 -07:00
Henry Cook
224e286dd3
New uncore config objects. Backends get their own file. Simplify fpga uncore.
2014-04-26 19:46:11 -07:00
Henry Cook
3d4273954a
TileLinkIO.GrantAck -> TileLinkIO.Finish
2014-04-26 15:19:25 -07:00