Rimas Avizienis
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63060bc0a8
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minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc)
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2013-01-23 19:27:53 -08:00 |
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Henry Cook
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6b00e7ff74
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New TileLink bundle names
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2013-01-21 17:18:23 -08:00 |
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Henry Cook
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a2fa3fd04d
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Refactored packet headers/payloads
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2013-01-15 15:50:37 -08:00 |
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Henry Cook
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e1225c5114
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standardize IO naming convention
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2013-01-07 13:41:36 -08:00 |
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Henry Cook
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261e14f831
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Refactored uncore conf
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2013-01-07 13:41:36 -08:00 |
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Andrew Waterman
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78868f6075
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add config option to trade mul/div area for speed
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2013-01-06 03:47:17 -08:00 |
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Andrew Waterman
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ce9f4881d2
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remove broken multiplier early out
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2013-01-06 03:47:00 -08:00 |
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Andrew Waterman
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05f19b21d0
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merge multiplier and divider
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2012-12-12 02:22:47 -08:00 |
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Andrew Waterman
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c921fc34a9
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merge ALU left and right shifters
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2012-12-12 02:22:34 -08:00 |
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Andrew Waterman
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f5c53ce35d
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add ecc support to d$ data rams
i haven't injected errors yet; it may well be incorrect.
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2012-12-11 15:58:53 -08:00 |
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Andrew Waterman
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3f59e439ef
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fix d$ tag raw hazard
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2012-12-07 15:14:20 -08:00 |
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Andrew Waterman
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e9752f1d72
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pipeline host pcr access
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2012-12-06 14:22:07 -08:00 |
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Andrew Waterman
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4dda38204f
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fix d$ reset bug
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2012-12-06 03:13:22 -08:00 |
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Andrew Waterman
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290d3d226c
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fix AMO and store bypass bugs
thanks, torture tester
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2012-12-06 02:07:52 -08:00 |
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Andrew Waterman
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4608660f6e
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torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
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2012-12-04 05:57:53 -08:00 |
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Andrew Waterman
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90cae54ac4
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fix D$ read/write concurrency bug
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2012-11-27 02:42:27 -08:00 |
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Andrew Waterman
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9c857b83f0
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refactor PCR file
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2012-11-27 01:28:06 -08:00 |
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Andrew Waterman
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64674d4d39
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clean up PTW and support PADDR_BITS < VADDR_BITS
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2012-11-26 20:38:45 -08:00 |
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Andrew Waterman
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608f65e716
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don't wastefully read 2x the bits from D$ RAMs
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2012-11-26 20:34:30 -08:00 |
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Andrew Waterman
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352bb464b5
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clock gate X/M and M/W store data registers
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2012-11-26 20:33:41 -08:00 |
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Andrew Waterman
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8a6ff5f9aa
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fix D$ writeback bug
I swear I did this last week... perhaps I am finally losing it!
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2012-11-25 19:46:48 -08:00 |
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Andrew Waterman
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de2f28193a
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get rid of more global constants
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2012-11-25 04:24:25 -08:00 |
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Andrew Waterman
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c036cdc1ea
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add option for 2-cycle load-use delay
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2012-11-24 22:01:08 -08:00 |
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Andrew Waterman
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b514c7b725
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clean up I$ parity code
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2012-11-24 22:00:43 -08:00 |
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Andrew Waterman
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55082e45c4
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add AVec, which automatically infers element type
should consider modifying Vec as such
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2012-11-24 18:19:28 -08:00 |
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Andrew Waterman
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2b26082132
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use 1r1w ram for tags; merge tags & permissions
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
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2012-11-20 04:09:26 -08:00 |
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Andrew Waterman
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72f94d1141
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fix virtual address sign extension detection
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2012-11-20 04:06:57 -08:00 |
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Andrew Waterman
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30038bda8a
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bypass stores to subsequent loads
since we handle subword stores as RMW operations, this occurs frequently
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2012-11-20 01:33:32 -08:00 |
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Yunsup Lee
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395e4e3dd6
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andrew'x fix for D$ corner case in writeback->abort->probe
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2012-11-18 03:11:06 -08:00 |
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Yunsup Lee
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06eeb90e2a
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vector unit interfaces to the new D$
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2012-11-17 20:07:41 -08:00 |
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Yunsup Lee
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81d711e892
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fix D$ bug; now D$ doesn't respond to prefetches
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2012-11-17 20:06:13 -08:00 |
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Andrew Waterman
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29bc361d6c
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remove global constants; disentangle hwacha a bit
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2012-11-17 17:24:08 -08:00 |
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Andrew Waterman
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5a7777fe4d
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clock gate integer datapath more aggressively
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2012-11-17 06:48:44 -08:00 |
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Andrew Waterman
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cc067026a2
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pipeline D$ response -> FPU regfile
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2012-11-17 06:48:11 -08:00 |
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Andrew Waterman
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e68b039133
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fix misc. D$ control bugs
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2012-11-17 06:47:27 -08:00 |
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Andrew Waterman
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dad7b71062
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provide cmd/addr with cache response
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2012-11-16 21:26:12 -08:00 |
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Andrew Waterman
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cb8ac73045
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provide store data with cache response
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2012-11-16 21:15:13 -08:00 |
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Andrew Waterman
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9e010beffe
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fix D$ refill bug
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2012-11-16 21:05:29 -08:00 |
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Andrew Waterman
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8dce89703a
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new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
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2012-11-16 02:39:33 -08:00 |
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Andrew Waterman
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a90a1790a5
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improve tlb qor
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2012-11-16 01:59:38 -08:00 |
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Andrew Waterman
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ff8c736d94
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move icache invalidate out of request bundle
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2012-11-16 01:55:45 -08:00 |
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Andrew Waterman
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6d10115b19
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fix D$ tag width
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2012-11-15 16:46:39 -08:00 |
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Yunsup Lee
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be1980dd2d
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refactored vector queue interface
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2012-11-07 01:15:33 -08:00 |
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Yunsup Lee
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8764fe786a
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refactored vector tlb
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2012-11-06 23:53:52 -08:00 |
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Yunsup Lee
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9a02298f6f
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andrew's fix for tlb lockup
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2012-11-06 23:52:58 -08:00 |
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Andrew Waterman
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4d1ca8ba3a
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remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
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2012-11-06 08:13:44 -08:00 |
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Andrew Waterman
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e76892f758
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remove more global constants
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2012-11-06 02:55:45 -08:00 |
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Andrew Waterman
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c5b93798fb
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factor out more global constants
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2012-11-05 23:52:32 -08:00 |
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Yunsup Lee
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ee081d1671
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modify code to fix UFix := Bits error
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2012-11-05 01:35:55 -08:00 |
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Yunsup Lee
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2a25307a8f
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revamp the vector unit with the new frontend
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2012-11-05 01:35:55 -08:00 |
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