Henry Cook
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db5a060c7d
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fix io dir
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2013-04-10 13:47:30 -07:00 |
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Andrew Waterman
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8b439ef20d
|
only support setpcr/clearpcr of SR
the full PCR RMW support was wasted area/power
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2013-04-04 17:07:08 -07:00 |
|
Andrew Waterman
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d43f484feb
|
take interrupts on nonzero fromhost values
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2013-04-04 17:07:08 -07:00 |
|
Andrew Waterman
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d4a3351cfc
|
expose pending interrupts in status register
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2013-04-04 17:07:08 -07:00 |
|
Henry Cook
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95f0a688e9
|
Merge branch 'release-xacts'
Conflicts:
src/htif.scala
src/icache.scala
src/nbdcache.scala
src/tile.scala
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2013-03-20 17:37:50 -07:00 |
|
Henry Cook
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6d2541aced
|
nTiles -> nClients in LogicalNetworkConfig
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2013-03-20 14:12:36 -07:00 |
|
Andrew Waterman
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5b9f938263
|
correctly sign-extend badvaddr, epc, and ebase
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2013-01-24 17:54:59 -08:00 |
|
Henry Cook
|
e1225c5114
|
standardize IO naming convention
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2013-01-07 13:41:36 -08:00 |
|
Andrew Waterman
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e9752f1d72
|
pipeline host pcr access
|
2012-12-06 14:22:07 -08:00 |
|
Andrew Waterman
|
4608660f6e
|
torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
|
2012-12-04 05:57:53 -08:00 |
|
Andrew Waterman
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9c857b83f0
|
refactor PCR file
|
2012-11-27 01:28:06 -08:00 |
|
Andrew Waterman
|
29bc361d6c
|
remove global constants; disentangle hwacha a bit
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2012-11-17 17:24:08 -08:00 |
|
Andrew Waterman
|
5a7777fe4d
|
clock gate integer datapath more aggressively
|
2012-11-17 06:48:44 -08:00 |
|
Andrew Waterman
|
7380c9fe60
|
aggressively clock gate int and fp datapaths
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2012-11-04 16:40:14 -08:00 |
|
Andrew Waterman
|
5773cbb68a
|
rejigger htif to use UncoreConfiguration
|
2012-10-18 17:26:03 -07:00 |
|
Henry Cook
|
88ac5af181
|
Merged consts-as-traits
|
2012-10-16 16:32:35 -07:00 |
|
Andrew Waterman
|
fc648d13a1
|
remove old Mux1H; add implicit conversions
|
2012-10-16 02:24:37 -07:00 |
|
Andrew Waterman
|
661f8e635b
|
merge I$, ITLB, BTB into Frontend
|
2012-10-16 02:24:37 -07:00 |
|
Henry Cook
|
8970b635b2
|
improvements to implicit RocketConfiguration parameter
|
2012-10-15 16:29:49 -07:00 |
|
Henry Cook
|
9025d0610c
|
first pass at configuration object passed as implicit parameter
|
2012-10-07 22:37:29 -07:00 |
|
Henry Cook
|
dfdfddebe8
|
constants as traits
|
2012-10-07 22:20:03 -07:00 |
|
Andrew Waterman
|
b94e6915ab
|
refactor IPIs; use new tohost/fromhost protocol
|
2012-08-03 19:00:34 -07:00 |
|
Andrew Waterman
|
130fa95ed6
|
expand HTIF's PCR register space
|
2012-07-27 14:52:39 -07:00 |
|
Andrew Waterman
|
4e44ed7400
|
allow back pressure on IPI requests
|
2012-07-17 22:55:40 -07:00 |
|
Huy Vo
|
fd95159837
|
INPUT/OUTPUT orderring swapped
|
2012-07-12 18:16:57 -07:00 |
|
Huy Vo
|
04304fe788
|
moving util out into Chisel standard library
|
2012-06-06 12:51:26 -07:00 |
|
Andrew Waterman
|
7f6319047e
|
update to new scala/chisel/Mem
|
2012-06-06 02:47:22 -07:00 |
|
Huy Vo
|
7408c9ab69
|
removing wires
|
2012-05-24 10:42:39 -07:00 |
|
Andrew Waterman
|
a2f6d01c1b
|
add programmable coreid register
|
2012-05-09 03:09:22 -07:00 |
|
Andrew Waterman
|
e0e1cd5d32
|
add IPIs and an IPI test
IPIs are routed through the HTIF, which seems weird, but that makes it
so cores can bring each other out of reset with IPIs.
|
2012-05-08 22:58:00 -07:00 |
|
Andrew Waterman
|
86d56ff67b
|
refactor cpu/i$/d$ into Tile (rather than Top)
|
2012-03-24 16:57:28 -07:00 |
|
Andrew Waterman
|
3a487ac89b
|
improve htif<->pcr interface
|
2012-03-24 16:57:28 -07:00 |
|
Andrew Waterman
|
54fa6f660d
|
new supervisor mode
|
2012-03-24 13:03:31 -07:00 |
|
Yunsup Lee
|
8c50c81b81
|
drop vec_irq_aux pcr register, now everything goes through badvaddr
|
2012-03-17 14:03:57 -07:00 |
|
Yunsup Lee
|
b19d783fbd
|
add vector irq handler
|
2012-03-14 14:15:28 -07:00 |
|
Yunsup Lee
|
040d62f372
|
refactored vector exception handling interface
|
2012-03-13 23:45:34 -07:00 |
|
Yunsup Lee
|
b100544b25
|
datapath to read out vector state
|
2012-03-13 23:45:34 -07:00 |
|
Yunsup Lee
|
a1b30282dd
|
major refactoring on vector exception interface
|
2012-03-09 01:09:22 -08:00 |
|
Yunsup Lee
|
d4ec7ff4d9
|
refined vector exception interface
|
2012-03-03 16:11:54 -08:00 |
|
Yunsup Lee
|
1054cec087
|
add vec countq interface
|
2012-03-02 00:43:32 -08:00 |
|
Huy Vo
|
5b0f7ccf68
|
updating rocket code to lastest version of chisel, passes assembly tests in C++ and Verilog as long as you dont use the vector unit
|
2012-02-26 17:24:08 -08:00 |
|
Yunsup Lee
|
94ba32bbd3
|
change package name and sbt project name to rocket
|
2012-02-25 17:09:26 -08:00 |
|
Yunsup Lee
|
946e0c6e4e
|
add vector exception infrastructure
|
2012-02-25 16:37:56 -08:00 |
|
Andrew Waterman
|
7034c9be65
|
new htif protocol and implementation
You must update your fesvr and isasim!
|
2012-02-19 23:15:45 -08:00 |
|
Andrew Waterman
|
1b5e39e7fc
|
fix bug in BTB
a BTB update followed by a taken branch could cause incorrect control flow.
|
2012-02-15 21:36:08 -08:00 |
|
Andrew Waterman
|
725190d0ee
|
update to new chisel
|
2012-02-11 17:20:33 -08:00 |
|
Yunsup Lee
|
f47d888feb
|
vvcfgivl and vsetvl works
|
2012-02-09 02:35:21 -08:00 |
|
Andrew Waterman
|
128ec567ed
|
make BTB fully associative; don't use it for JALR
JALR created a long path from the ALU in execute stage
to an address comparator to the next-PC mux. the benfit
was close to nil, anyway.
|
2012-02-09 01:34:00 -08:00 |
|
Yunsup Lee
|
fcc8081c4d
|
hook up the vector command queue
|
2012-02-09 01:28:16 -08:00 |
|
Andrew Waterman
|
b3f6f9a5fd
|
fix BTB misprediction check for negative addresses
also index BTB with PC, not PC+4
|
2012-02-08 15:05:28 -08:00 |
|