Andrew Waterman
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5b9f938263
|
correctly sign-extend badvaddr, epc, and ebase
|
2013-01-24 17:54:59 -08:00 |
|
Rimas Avizienis
|
63060bc0a8
|
minor tweaks for eos18 tapeout (SRAM r/w port ordering, etc)
|
2013-01-23 19:27:53 -08:00 |
|
Henry Cook
|
6b00e7ff74
|
New TileLink bundle names
|
2013-01-21 17:18:23 -08:00 |
|
Henry Cook
|
a2fa3fd04d
|
Refactored packet headers/payloads
|
2013-01-15 15:50:37 -08:00 |
|
Henry Cook
|
e1225c5114
|
standardize IO naming convention
|
2013-01-07 13:41:36 -08:00 |
|
Henry Cook
|
261e14f831
|
Refactored uncore conf
|
2013-01-07 13:41:36 -08:00 |
|
Andrew Waterman
|
78868f6075
|
add config option to trade mul/div area for speed
|
2013-01-06 03:47:17 -08:00 |
|
Andrew Waterman
|
ce9f4881d2
|
remove broken multiplier early out
|
2013-01-06 03:47:00 -08:00 |
|
Andrew Waterman
|
05f19b21d0
|
merge multiplier and divider
|
2012-12-12 02:22:47 -08:00 |
|
Andrew Waterman
|
c921fc34a9
|
merge ALU left and right shifters
|
2012-12-12 02:22:34 -08:00 |
|
Andrew Waterman
|
f5c53ce35d
|
add ecc support to d$ data rams
i haven't injected errors yet; it may well be incorrect.
|
2012-12-11 15:58:53 -08:00 |
|
Andrew Waterman
|
3f59e439ef
|
fix d$ tag raw hazard
|
2012-12-07 15:14:20 -08:00 |
|
Andrew Waterman
|
e9752f1d72
|
pipeline host pcr access
|
2012-12-06 14:22:07 -08:00 |
|
Andrew Waterman
|
4dda38204f
|
fix d$ reset bug
|
2012-12-06 03:13:22 -08:00 |
|
Andrew Waterman
|
290d3d226c
|
fix AMO and store bypass bugs
thanks, torture tester
|
2012-12-06 02:07:52 -08:00 |
|
Andrew Waterman
|
4608660f6e
|
torture revealed a couple bugs
FP loads/stores with certain negative offsets could cause illegal rounding
mode traps, and x's were cropping up in situations that are benign in HW.
|
2012-12-04 05:57:53 -08:00 |
|
Andrew Waterman
|
90cae54ac4
|
fix D$ read/write concurrency bug
|
2012-11-27 02:42:27 -08:00 |
|
Andrew Waterman
|
9c857b83f0
|
refactor PCR file
|
2012-11-27 01:28:06 -08:00 |
|
Andrew Waterman
|
64674d4d39
|
clean up PTW and support PADDR_BITS < VADDR_BITS
|
2012-11-26 20:38:45 -08:00 |
|
Andrew Waterman
|
608f65e716
|
don't wastefully read 2x the bits from D$ RAMs
|
2012-11-26 20:34:30 -08:00 |
|
Andrew Waterman
|
352bb464b5
|
clock gate X/M and M/W store data registers
|
2012-11-26 20:33:41 -08:00 |
|
Andrew Waterman
|
8a6ff5f9aa
|
fix D$ writeback bug
I swear I did this last week... perhaps I am finally losing it!
|
2012-11-25 19:46:48 -08:00 |
|
Andrew Waterman
|
de2f28193a
|
get rid of more global constants
|
2012-11-25 04:24:25 -08:00 |
|
Andrew Waterman
|
c036cdc1ea
|
add option for 2-cycle load-use delay
|
2012-11-24 22:01:08 -08:00 |
|
Andrew Waterman
|
b514c7b725
|
clean up I$ parity code
|
2012-11-24 22:00:43 -08:00 |
|
Andrew Waterman
|
55082e45c4
|
add AVec, which automatically infers element type
should consider modifying Vec as such
|
2012-11-24 18:19:28 -08:00 |
|
Andrew Waterman
|
2b26082132
|
use 1r1w ram for tags; merge tags & permissions
setting the dirty bit now allocates an MSHR (to reuse the existing datapath)
|
2012-11-20 04:09:26 -08:00 |
|
Andrew Waterman
|
72f94d1141
|
fix virtual address sign extension detection
|
2012-11-20 04:06:57 -08:00 |
|
Andrew Waterman
|
30038bda8a
|
bypass stores to subsequent loads
since we handle subword stores as RMW operations, this occurs frequently
|
2012-11-20 01:33:32 -08:00 |
|
Yunsup Lee
|
395e4e3dd6
|
andrew'x fix for D$ corner case in writeback->abort->probe
|
2012-11-18 03:11:06 -08:00 |
|
Yunsup Lee
|
06eeb90e2a
|
vector unit interfaces to the new D$
|
2012-11-17 20:07:41 -08:00 |
|
Yunsup Lee
|
81d711e892
|
fix D$ bug; now D$ doesn't respond to prefetches
|
2012-11-17 20:06:13 -08:00 |
|
Andrew Waterman
|
29bc361d6c
|
remove global constants; disentangle hwacha a bit
|
2012-11-17 17:24:08 -08:00 |
|
Andrew Waterman
|
5a7777fe4d
|
clock gate integer datapath more aggressively
|
2012-11-17 06:48:44 -08:00 |
|
Andrew Waterman
|
cc067026a2
|
pipeline D$ response -> FPU regfile
|
2012-11-17 06:48:11 -08:00 |
|
Andrew Waterman
|
e68b039133
|
fix misc. D$ control bugs
|
2012-11-17 06:47:27 -08:00 |
|
Andrew Waterman
|
dad7b71062
|
provide cmd/addr with cache response
|
2012-11-16 21:26:12 -08:00 |
|
Andrew Waterman
|
cb8ac73045
|
provide store data with cache response
|
2012-11-16 21:15:13 -08:00 |
|
Andrew Waterman
|
9e010beffe
|
fix D$ refill bug
|
2012-11-16 21:05:29 -08:00 |
|
Andrew Waterman
|
8dce89703a
|
new D$ with better QoR and AMO pipelining
Vector unit is disabled because nack handling needs to be fixed.
|
2012-11-16 02:39:33 -08:00 |
|
Andrew Waterman
|
a90a1790a5
|
improve tlb qor
|
2012-11-16 01:59:38 -08:00 |
|
Andrew Waterman
|
ff8c736d94
|
move icache invalidate out of request bundle
|
2012-11-16 01:55:45 -08:00 |
|
Andrew Waterman
|
6d10115b19
|
fix D$ tag width
|
2012-11-15 16:46:39 -08:00 |
|
Yunsup Lee
|
be1980dd2d
|
refactored vector queue interface
|
2012-11-07 01:15:33 -08:00 |
|
Yunsup Lee
|
8764fe786a
|
refactored vector tlb
|
2012-11-06 23:53:52 -08:00 |
|
Yunsup Lee
|
9a02298f6f
|
andrew's fix for tlb lockup
|
2012-11-06 23:52:58 -08:00 |
|
Andrew Waterman
|
4d1ca8ba3a
|
remove more global consts; refactor DTLBs
D$ now contains DTLB. provide full VAddr with initial request.
VU now has its own DTLBs.
|
2012-11-06 08:13:44 -08:00 |
|
Andrew Waterman
|
e76892f758
|
remove more global constants
|
2012-11-06 02:55:45 -08:00 |
|
Andrew Waterman
|
c5b93798fb
|
factor out more global constants
|
2012-11-05 23:52:32 -08:00 |
|
Yunsup Lee
|
ee081d1671
|
modify code to fix UFix := Bits error
|
2012-11-05 01:35:55 -08:00 |
|