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Author SHA1 Message Date
Andrew Waterman 69441930b5 Rationalize ALU function encoding 
MULHSU and MULHU should match their ISA funct3 encodings to slightly
reduce HW cost.
 2018-02-06 14:00:37 -08:00
solomatnikov 5294523551
Keep io.cpu.s1_data for visibility (#1218) 2018-01-31 14:31:42 -08:00
Henry Cook 7dad486707 util: updates to internal Generator API 2018-01-30 15:19:37 -08:00
Henry Cook bd50a1a4bc config: remove deprecated Parameters.root 2018-01-30 11:52:44 -08:00
Henry Cook 46751bedeb config: MapParameters are back in style 2018-01-30 11:52:44 -08:00
Jacob Chang f4853c4f63
Add cover properties to Core CSRs (#1212) 2018-01-30 00:01:19 -08:00
Andrew Waterman b5ff853e86
Sign-extend the depc CSR (#1209) 2018-01-26 12:07:33 -08:00
Andrew Waterman 8d8e4e1399
Merge pull request #1196 from freechipsproject/interrupt-cover 
Cover all exceptions and interrupts
 2018-01-25 18:06:13 -08:00
Andrew Waterman d2399b6d0e Cover all exceptions and interrupts 2018-01-25 16:14:56 -08:00
Jacob Chang a749326deb
Add cover points to registers (#1208) 2018-01-24 21:37:24 -08:00
Andrew Waterman 7a0252fdfc Add some covers for FPU structural hazards 2018-01-23 16:32:03 -08:00
Andrew Waterman a2ca82f92c Add VM covers 2018-01-23 16:13:35 -08:00
Wesley W. Terpstra c32150b994
ResetCatchAndSync: work also in the context of a RawModule (#1202) 2018-01-19 19:45:52 -08:00
Wesley W. Terpstra f6f5606f8e
diplomacy: run user instantiate() method after nodes are initialized (#1198) 2018-01-18 14:57:47 -08:00
Henry Cook 5cc1411e14
Merge pull request #1199 from freechipsproject/require-messages 
rocket: add address to tlb permissions require msgs
 2018-01-18 14:53:25 -08:00
Jack Koenig bf5dd6dac3
Replace Parameters in cover with globally setable implementation (#1200) 
This change is made in anticipation of a proper coverage library
 2018-01-18 14:45:36 -08:00
Henry Cook 24c1235500 rocket: add address to tlb permissions require msgs 2018-01-18 10:31:51 -08:00
Wesley W. Terpstra 5854fb5f7c
SourceShrinker improvements (#1197) 
* SourceShrinker: preserve FIFO guarantees of slaves

* tilelink: document that Releases can use TtoT, BtoB, and NtoN

TtoT is needed for write-through caches.
 2018-01-17 18:02:19 -08:00
Megan Wachs 338e453a91
JTAG: Use new withClock way of overriding clocks (#1072) 
* JTAG: Use new withClock way of overriding clocks

the override clock way is deprecated

* JTAG: use withClock instead of override clock

* JTAG:  extend Module for ClockedCounter

* JTAG: Don't use deprecated clock constructs

* JTAG: Remove another override_clock

* Rename "NegativeEdgeLatch"

because it's not a latch, it's just a register on the negative edge of the clock.

* Use the appropriately named NegEdgeReg

* JTAG: Rename another NegativeEdgeLatch
 2018-01-17 13:59:05 -08:00
Schuyler Eldridge 355d3b15e8 Merge 'origin/master' into auto-plusargs 2018-01-16 15:45:53 -05:00
Jacob Chang 80ca018e3a
Add cover points for BusErrorUnit (#1193) 2018-01-15 18:00:29 -08:00
Schuyler Eldridge 04af785a5f Emit plusArgs for unit tests 
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
 2018-01-15 17:54:40 -05:00
Schuyler Eldridge 09c1d034fa Explicitly name PlusArg serializers as *_cHeader 
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
 2018-01-15 17:00:12 -05:00
Schuyler Eldridge cfd49f87c1 Use longname for ElaborationArtefact emission 
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
 2018-01-15 16:55:13 -05:00
Schuyler Eldridge e52d52ae99 Link PlusArg to emulator command line options 
- adds a mutable singleton (PlusArgArtefacts) to store information
  about Rocket PlusArgs
- adds methods to PlusArgArtefacts to emit C snippets that are
  consumed by emulator.cc for correct argument parsing and help text
  generation
- emits snippets in $(CONFIG).plusArgs via BaseCoreplex-set
  ElaborationArtefacts
- modify emulator/Makefrag-verilator to include $(CONFIG).plusArgs
- cleanup help text (docstring) for existing PlusArgs

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@gmail.com>
 2018-01-15 14:32:55 -05:00
Megan Wachs 5fe0bb0d6a Merge remote-tracking branch 'origin/master' into refactored_rbb 2018-01-09 21:34:14 -08:00
Henry Cook f5211765e9
Merge pull request #1177 from freechipsproject/dont-touch-2 
Make more use of chisel3.experimental.DontTouch
 2018-01-09 15:13:55 -08:00
pentin-as c152962642 Dual-port RAM replaced with single-port RAM for tag_array in HellaCache (#1181) 
In accordance with https://github.com/freechipsproject/chisel3/issues/752
 2018-01-09 13:06:43 -08:00
Henry Cook 15c54b1c5a tile: intSinkNode belongs in HasExternalInterrupts 2018-01-08 19:38:10 -08:00
Henry Cook 11e5b620f8 tile: disable more monitors on slave port 2018-01-08 18:42:25 -08:00
Henry Cook 5075a93e6c util: dontTouch work-around for zero width aggregates 2018-01-08 15:58:28 -08:00
Albert Huntington 7fc8337cdb
Merge pull request #1180 from freechipsproject/addrwregdesc 
Allow rwReg to pass name and description to RegField for documentation.
 2018-01-08 09:44:44 -08:00
Megan Wachs a530646d15 Merge remote-tracking branch 'origin/master' into refactored_rbb 2018-01-08 09:11:27 -08:00
Henry Cook 4fd4ae38e3
Merge pull request #1176 from freechipsproject/fix-tl-port 
Fix TL MMIO port
 2018-01-05 20:37:44 -08:00
Megan Wachs e6661a6982 Debug regressions: use a plusarg to enable remote bitbang. 2018-01-05 17:08:21 -08:00
Albert Huntington 8425086f98 Allow rwReg to pass name and description to RegField for documentation. 2018-01-05 16:59:58 -08:00
Megan Wachs 4449dd0baa Debug regressions: Add necessary config scripts 2018-01-05 16:03:59 -08:00
Megan Wachs e82328336e Add in a SimJTAG to connect to OpenOCD's remote-bitbang interface. 
This is simpler than JTAGVPI and is supported better by Verilor.
It is also the same thing Spike uses.
 2018-01-05 16:02:52 -08:00
Henry Cook b77b93b0b4 util: dontTouchPortsExcept 2018-01-05 14:06:00 -08:00
Andrew Waterman 000cde2f8a Make ErrorDevice UNCACHEABLE instead of UNCACHED 
...even though it still supports Acquire.  This avoids needing to flush
the D$ on FENCE.I because of the presence of the ErrorDevice.
 2018-01-05 14:00:42 -08:00
Andrew Waterman ad0b9a0b1b Reduce cases in which FENCE.I must flush D$ 
Memory regions that are uncacheable or have get/put effects should not
reside in the D$, so there is no need to flush them.
 2018-01-05 13:58:14 -08:00
Henry Cook 4853d1355f rocket: dontTouch HellaCache.io.cpu.resp 2018-01-05 12:50:24 -08:00
Henry Cook 847efde385 coreplex: dontTouch the tile_inputs wire 2018-01-05 12:47:41 -08:00
Wesley W. Terpstra f749e986cf coreplex: fix TL MMIO port example 2018-01-05 12:29:47 +01:00
Andrew Waterman 206892899f
Merge pull request #1171 from freechipsproject/fix-msb-check 
Enforce physical-address canonicalization
 2018-01-03 12:06:18 -08:00
Andrew Waterman ee1a9485df Enforce physical-address canonicalization 
When xLen > paddrBits, enforce that physical addresses are zero-extended.
This works by checking that the _virtual_ address is _sign_-extended, then
checking that its sign is positive.
 2018-01-02 18:47:30 -08:00
Andrew Waterman 7c9a1b0265 Correctly check for virtual-address canonicalization 
The previous check was necessary but not sufficient.
 2018-01-02 18:41:25 -08:00
Henry Cook 320900f76c tile: BaseTileModule => BaseTileModuleImp 2018-01-02 17:55:54 -08:00
Henry Cook b0e1bc3071 tile: cake reduction 
* merge HasScratchpadSlavePort into RocketTile
* merge CanHaveSharedFPUModule into BaseTileModule
 2018-01-02 17:49:08 -08:00
Henry Cook efe7165b54 tile: BaseTile refactor, pt 2 
* 2 layer cake
* no more bundle traits, only call to IO
 2018-01-02 15:37:31 -08:00
Henry Cook 1579ddb97e tile: removed RocketTileWrapper. RocketTile now HasCrossing. 2017-12-28 14:00:13 -08:00
Henry Cook 1cd018546c tile: BaseTile refactor, pt 1 
* Make dts generation reusable across tile subclasses
* First attempt to standardize tile IO nodes and connect methods
* hartid => hartId when talking about scala Ints
 2017-12-26 11:04:15 -08:00
Henry Cook ba6dd160a3 diplomacy: allow access to sram Device info 2017-12-22 19:00:43 -08:00
Henry Cook d9c5ec4f7b coreplex: HasTiles supplies def tileParams 2017-12-20 17:18:55 -08:00
Henry Cook ddaeedf2d0 coreplex: make HasTiles more generic 
HasTiles now deals with only extremely general tile IOs.
Some RocketTiles specific behavior moved into RocketCoreplex.
BaseTile now has optional LocalInterruptNode.
 2017-12-20 17:18:55 -08:00
Henry Cook 895c4b9261
Revert "ICache: stores to the ITIM have effects (shrinking valid ITIM data) (#1144)" (#1162) 
This reverts commit a542ae687e.
 2017-12-19 12:16:26 -08:00
Megan Wachs 74d9326ebc
JTAG: Revert to Chisel._ for Issue 1160 (#1161) 
* JTAG: Revert to Chisel._ for Issue 1160

* JTAG: Revert to Chisel._ for Issue 1160

* jtag: revert everything to Chisel._

* jtag: Revert all modules to Chisel._ vs chisel3, due to FIRRTL issues with chisel3 generated code
 2017-12-18 21:02:31 -08:00
Henry Cook a31ba2ea2e
diplomacy: LazyModule factory uses ValName (#1159) 
* diplomacy: LazyModule factory uses ValName
 2017-12-18 15:40:30 -08:00
Jacob Chang 09160d0cd5
Changed label for DCache and ICache error covers + take away exclusio… (#1155) 
* Changed label for DCache and ICache error covers + take away exclusion that shouldn't be there

* rocket: add d-channel error to I$
 2017-12-13 20:16:36 -08:00
Wesley W. Terpstra a542ae687e
ICache: stores to the ITIM have effects (shrinking valid ITIM data) (#1144) 2017-12-08 17:35:14 -08:00
Wesley W. Terpstra c2a0319dc4
Merge pull request #1151 from freechipsproject/error-atoms 
Error atomics
 2017-12-08 17:34:55 -08:00
Wesley W. Terpstra efc793d52e CloneModule: must be public to be used in pattern matches 2017-12-08 14:57:08 -08:00
Wesley W. Terpstra 2ca03384ec diplomacy: skip anonymous class names 2017-12-08 14:36:12 -08:00
Jack Koenig 588dacec17
Bump Chisel and Firrtl (#1134) 2017-12-08 14:22:18 -08:00
Wesley W. Terpstra 18b8a61775 Error device: require explicit control of atomic and transfer sizes 2017-12-08 13:41:09 -08:00
Wesley W. Terpstra 6a0150aad7 Error device: mark executable to support testing erroneous I$ refill 2017-12-08 12:38:06 -08:00
Andrew Waterman 676110bc1f Add cover for a1ebe6da4d 2017-12-07 21:03:42 -08:00
Andrew Waterman a1ebe6da4d Prevent frontend deadlock fetching from uncacheable memory 
After detecting a corrupted BTB, don't speculatively update it until
the next non-speculative fetch.  This prevents the frontend from replaying
forever.
 2017-12-07 18:56:06 -08:00
Jacob Chang ec3789b365
Add Cross Cover Property Library (#1149) 
Add cover points related to memory error to I/D Cache
 2017-12-07 18:46:10 -08:00
Andrew Waterman 5c204f98d5
When writing full words to ITIM, ECC errors are correctable (#1148) 
* When writing full words to ITIM, ECC errors are correctable

* Disable D$ tag reset state machine when using scratchpad
 2017-12-07 16:00:26 -08:00
Richard Xia 50de991f18 Fix typo in breakpoint cover property. 2017-12-04 14:04:24 -08:00
Wesley W. Terpstra b8098d18be
diplomacy: remove the :=? operator in favour of magic :*=* (#1139) 
The reason for the :=? operator was for when you have an adapter chain
whose direction of cardinality you could not know. We used explicit
directives to tell these compositions which way to go.

Unfortunately, that makes the API leaky. You think the chain of adapters
is just one adapter, but you have to use strange Cardinality scopes to
use it. That's just bad.

The new :*=* just automagically figures it out from the graph.
 2017-12-01 18:28:37 -08:00
Wesley W. Terpstra dedf396915
groundtest: connect the ibus to a fictitious master (#1140) 2017-12-01 18:28:24 -08:00
Henry Cook 71ddd797bf
Merge pull request #1138 from freechipsproject/cover_tag_ecc_error_during_fence_i 
Added coverage point to cover the case when ECC error happens during …
 2017-12-01 18:00:11 -08:00
Gleb Gagarin 7c2df9f0bf Cover the case when there is an ECC error in DCache data array during fence.i execution 2017-12-01 16:28:28 -08:00
Gleb Gagarin 74bd61c556 Added coverage point to cover the case when ECC error happens during fence.i execution 2017-12-01 15:50:31 -08:00
Wesley W. Terpstra 8781d2b2e7 diplomacy: provide a val name for all LazyModule constructions 2017-12-01 11:28:21 -08:00
Wesley W. Terpstra fe8d557751 PeripheryBus: automatically disappear when not used 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra 93c8010aca FrontBus: automatically disappear when not used 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra e489c4226e diplomacy: remove node arity and allow empty Nexus nodes (Xbars) 
This removes the mostly obsolete 'numIn/Out' range restrictions on nodes.
It also makes it possible to connect optional crossbars that disappear.

val x = TLXbar()
x := master
slave := x

val y = TLXbar()
x :=* y // only connect y if it gets used

This will create crossbar x, but crossbar y will disappear.
 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra 6a25a3b7ac tilelink: we can have helper objects for terminal nodes now too! 
The new rule is you should have an object.apply method if you only have a
single .node.
 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra 2092cb4ec8 diplomacy: reprotect Node bundles after module construction is completed 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra fdeed7bbb3 unittest: add an API for describing LazyModule unit tests 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra cc789e9063 diplomacy: protect more of the unstable API 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra 8ed9e78903 diplomacy: support cloning of LazyModules 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra b43bcdfcd1 CloneModule: beat chisel into submission 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra 1f23f9f865 diplomacy: categorize parameter resolution by direction+side 2017-12-01 11:26:59 -08:00
Wesley W. Terpstra fbbfc9c096 diplomacy: include edge type in inward/outward node handles 
This is necessary capture the node implementation in the handle,
which is in turn necessary to support cloning a Node.
 2017-12-01 11:26:58 -08:00
Wesley W. Terpstra 35506279af regmapper: fix d_ready => d_bits loop in RegField.bytes 
RegField.bytes updates only those bytes which are written every cycle.
However, there was a bug that it would try to return the updated value on reads.
This led to another TL-spec violating combinational path, just like the Debug module.
 2017-11-30 16:38:45 -08:00
Wesley W. Terpstra fc1f5be316 Debug: fix a latent combinational loop (d_ready => d_bits) 
When passed a Wire, WNotify outputs that wire on reads wire => d_bits.
Furthermore, it updates the Wire when a write occures d_ready => wire.

These registers should be returning undefined value on read, anyway.
 2017-11-30 16:36:45 -08:00
Richard Xia a447343074
Merge pull request #1129 from freechipsproject/add-exception-cover-properties 
Add cover properties for exceptions in the core.
 2017-11-30 16:23:14 -08:00
Richard Xia 4bd9c477ea Add cover properties for ECALL exceptions. 2017-11-30 14:27:04 -08:00
Richard Xia 29c70501f2 Add cover properties for exceptions in the core. 2017-11-30 14:27:04 -08:00
Andrew Waterman 890528c641 Avoid data corruption under correctable tag error during flush 
This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable.  Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
 2017-11-29 16:09:44 -08:00
Andrew Waterman 34d86ef665 Revert "Avoid data corruption under correctable tag error during flush (#1130)" 
This reverts commit 44eb4d12b5.
 2017-11-29 16:09:30 -08:00
Andrew Waterman 44eb4d12b5 Avoid data corruption under correctable tag error during flush (#1130) 
This esoteric bug manifests if a tag-read error occurs when a FENCE.I is
executed, even if the error was correctable.  Subsequently, an attempt to
flush a dirty line may flush the wrong line's data.
 2017-11-29 09:42:00 -08:00
Megan Wachs f554ad7e2c debug: Remove workaround for Chisel 3 #527 2017-11-27 10:50:15 -08:00
Andrew Waterman 5155eb6059
Don't emit writeback state machine logic for scratchpad (#1127) 
Firrtl can't DCE it because it would require analyzing the state machine.
 2017-11-22 18:40:02 -06:00
Wesley W. Terpstra 6f3ff634f2 DTS: collect common DTS nodes and move timebase-frequency to cores 
Putting the common DTS nodes into a shared object makes them get
emitted only one time. Plus it's better style.

timebase-frequency should really have been in the cpu nodes in the
first place according to the spec anyway. I was foolishly trying to
save bytes. However, now we really want it there in case it differs.
 2017-11-20 18:09:57 -08:00
Wesley W. Terpstra 3b299397db diplomacy: bind resources to outer-most binding 
This is probably the wrong thing to do, but it is expedient for now.
We need a better way to do cross-coreplex visibility.
 2017-11-20 17:42:08 -08:00