riscv/rocket-chip
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3d990bdbef
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160 Commits

Author SHA1 Message Date
Howard Mao
3d990bdbef workaround for Chisel3 name-aliasing issue 2016-03-30 19:15:22 -07:00
Howard Mao
7f8f138d6a fix addPendingBitWhenPartialWritemask 2016-03-24 20:01:50 -07:00
Palmer Dabbelt
c9e1b72972 Don't assign SInt(-1) to a UInt 2016-03-23 16:24:27 -07:00
Henry Cook
67e711844a index extraction bug 2016-03-10 17:37:40 -08:00
Palmer Dabbelt
8c7e29eacd Avoid generating 0-width UInts 
Chisel3 requires a 1-bit width to represent UInt(0).
 2016-03-10 17:37:40 -08:00
Henry Cook
93773a4496 Refactor L2 transaction trackers to each be capable of processing Voluntary Writebacks. 
To elide several races between reading and writing the metadata array for different types of transactions, all L2XactTrackers can now sink Voluntary Releases (writebacks from the L1 in the current implementation). These writebacks are merged with the ongoing transaction, and the merging tracker supplies an acknowledgment of the writeback in addition to its ongoing activities. This change involved another refactoring of the control logic for allocating new trackers and routing incoming Acquires and Releases. BroadcastHub uses the new routing logic, but still processes all voluntary releases through the VoluntaryReleaseTracker (not a problem because there are no metadata update races).

Closes #18
Closes #20
 2016-03-10 17:14:34 -08:00
Henry Cook
7eef3393f1 fix bug resulting in different g_types on tail beats in L2CacheBank.io.inner.grant 2016-03-02 14:11:45 -08:00
Henry Cook
57370bdf49 first and last on HasTileLinkData 2016-03-02 14:11:39 -08:00
Albert Magyar
ab30983aa9 Add support for per-way cache metadata 
Exposes new parameter field SplitMetadata to determine whether the metadata array in a particular cache is stored in a single SeqMem or with one SeqMem per way.

Closes #14
 2016-03-01 12:19:42 -08:00
Howard Mao
6d984273b7 finally fix all release assertions ... hopefully 2016-02-29 15:22:24 -08:00
Howard Mao
8873222e42 fix cache release assertion 2016-02-23 16:03:51 -08:00
Henry Cook
929d8e31f7 refactor ready/valid logic for routing release messages in the l2 2016-02-19 16:30:26 -08:00
Howard Mao
4ff1aea288 fix more Chisel3 deprecations 2016-01-14 14:55:45 -08:00
Andrew Waterman
a953ff384a Chisel3 compatibility: use more concrete types 2016-01-12 15:32:14 -08:00
Howard Mao
a48237f36d get rid of the rest of the PutBlock special casing in L2 2015-12-16 20:56:29 -08:00
Albert Magyar
922b1adc9c Add optional PLRU replacement to the L2 2015-12-16 10:00:56 -08:00
Howard Mao
ddc79674f9 fix some issues with cache request merging 2015-12-15 21:31:02 -08:00
Howard Mao
ee6514e4f4 make sure WritebackUnit sends correct probe addresses 2015-11-21 15:55:11 -08:00
Howard Mao
04383a31f5 Revert "make sure L2MetadataArray assigns unoccupied way if available" 
This reverts commit 1857f36c1e6f2b2859c724eea6ae3cfb2618f81b.
 2015-11-21 10:35:40 -08:00
Howard Mao
3c95afebc6 Shift set index for multi-bank configurations 
Prior to this commit, the L2 cache banks used the lower bits of the
block address as the set index. However, the lower bits are also used to
route addresses to different banks. As a result, in multi-bank
configurations, only a fraction of the sets in each bank could be
accessed. This commit fixes that problem by using the bits ahead of the
bank index as the set index, so that all sets in the cache can be
accessed.
 2015-11-20 23:24:57 -08:00
Howard Mao
24f7b9f472 make sure L2MetadataArray assigns unoccupied way if available 2015-11-19 10:45:54 -08:00
Henry Cook
2b977325e3 Make prefetch type available in a_type, issue probeInvalidates for putPrefetches 2015-11-16 23:26:13 -08:00
Henry Cook
0290635454 amo_shift_bits -> amo_shift_bytes 2015-11-16 19:07:58 -08:00
Henry Cook
64aaf71b06 L2AcquireTracker refactor to support merging Gets and Puts into Prefetches of the correct type. 
Transaction metadata for primary and seconday misses now stored in the secondary miss queue.

Added BuiltInAcquireBuilder factory.
 2015-11-16 18:10:09 -08:00
Henry Cook
03fa06e6e7 fix prefetch lockup on L2 hit 2015-11-15 12:51:34 -08:00
Howard Mao
e12efab423 skip meta_write state if no meta write pending 2015-11-13 13:50:35 -08:00
Howard Mao
7e7d688a01 make sure L2 passes no-alloc acquires through to outer memory 2015-11-12 15:40:58 -08:00
Howard Mao
7733fbe6a3 make sure no-alloc write still updates data array if there is a cache hit 2015-11-12 11:39:36 -08:00
Howard Mao
b59ce5fed4 make sure L2 waits for outer grant before sending grant for write request 2015-11-10 16:06:14 -08:00
Henry Cook
e3efc09b5b remove unnecessary UInt encode/decode on releaseMatches path 2015-11-05 17:20:03 -08:00
Henry Cook
3698153535 OHToUInt instead of PriorityEncoder on Acq/RelMatches signals in L2Bank 2015-11-03 14:31:35 -08:00
Henry Cook
f8594da1d3 depend on external cde library 2015-10-21 18:17:17 -07:00
Henry Cook
d391f97953 Minor refactor of StoreGen/AMOALU. Bugfix for 32b ops in L2's AMOALU. 2015-10-16 19:11:06 -07:00
Henry Cook
7fa3eb95e3 refactor tilelink params 2015-10-14 12:13:37 -07:00
Henry Cook
66ea39638e GlobalAddrMap 2015-10-14 00:23:28 -07:00
Henry Cook
31be6407ec Removed all traces of params 2015-10-14 00:23:28 -07:00
Andrew Waterman
3b1da4c57e Revert "replace remaining uses of Vec.fill" 
This reverts commit b6bb4e42127d1ed42b55ec8b859a4e074b347d47.
 2015-09-25 17:06:57 -07:00
Howard Mao
d1f2d40a90 replace remaining uses of Vec.fill 2015-09-24 17:50:09 -07:00
Andrew Waterman
24389a5257 Chisel3 compatibility fixes 2015-09-11 15:41:39 -07:00
Andrew Waterman
350d530766 Use Vec.fill, not Vec.apply, for Vec literals 2015-08-27 10:00:43 -07:00
Andrew Waterman
94287fed90 Avoid type-unsafe assignments 2015-08-27 09:57:36 -07:00
Andrew Waterman
05d311c517 Use Vec.apply, not Vec.fill, for type nodes 2015-08-27 09:47:02 -07:00
Andrew Waterman
798ddeb5f5 Chisel3 compatibility: use >>Int instead of >>UInt 
The latter doesn't contract widths anymore.
 2015-08-04 13:15:17 -07:00
Andrew Waterman
8f7b390353 UInt-> Bits; avoid mixed UInt/SInt code 2015-07-30 23:49:06 -07:00
Henry Cook
c70b495f6d moved buses to junctions repo 2015-07-29 18:04:30 -07:00
Andrew Waterman
a69c749249 Fix compilation with scala 2.11.6 
We forgot to specify return types on overloaded methods, and a previous
version of the scala compiler failed to flag this as an error.
 2015-07-28 16:24:45 -07:00
Andrew Waterman
3c0475e08b Add Wire() wrap 2015-07-15 20:24:03 -07:00
Andrew Waterman
2d6b3b2331 Don't use clone 2015-07-15 18:06:27 -07:00
Andrew Waterman
15cec0eab7 Vec(Reg) -> Reg(Vec) 2015-07-15 12:44:54 -07:00
Andrew Waterman
e76a9d3493 Chisel3: Don't mix Mux types 2015-07-11 14:05:39 -07:00