88cc91db75
Ignore way_en in MetadataArray for direct-mapped caches
2016-05-24 15:47:09 -07:00
f88b6932ce
don't add pending reads if data is already available
2016-04-06 15:43:21 -07:00
c292a07ace
Bugfix for merged voluntary releases in L2Cache.
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Track pending release beats for voluntary releases that are merged by Acquire Trackers.
Closes #23 and #24 .
2016-04-01 19:57:47 -07:00
d78066db5c
chisel3 fix for split metadata
2016-03-30 22:11:19 -07:00
3d990bdbef
workaround for Chisel3 name-aliasing issue
2016-03-30 19:15:22 -07:00
7f8f138d6a
fix addPendingBitWhenPartialWritemask
2016-03-24 20:01:50 -07:00
c9e1b72972
Don't assign SInt(-1) to a UInt
2016-03-23 16:24:27 -07:00
67e711844a
index extraction bug
2016-03-10 17:37:40 -08:00
8c7e29eacd
Avoid generating 0-width UInts
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Chisel3 requires a 1-bit width to represent UInt(0).
2016-03-10 17:37:40 -08:00
93773a4496
Refactor L2 transaction trackers to each be capable of processing Voluntary Writebacks.
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To elide several races between reading and writing the metadata array for different types of transactions, all L2XactTrackers can now sink Voluntary Releases (writebacks from the L1 in the current implementation). These writebacks are merged with the ongoing transaction, and the merging tracker supplies an acknowledgment of the writeback in addition to its ongoing activities. This change involved another refactoring of the control logic for allocating new trackers and routing incoming Acquires and Releases. BroadcastHub uses the new routing logic, but still processes all voluntary releases through the VoluntaryReleaseTracker (not a problem because there are no metadata update races).
Closes #18
Closes #20
2016-03-10 17:14:34 -08:00
7eef3393f1
fix bug resulting in different g_types on tail beats in L2CacheBank.io.inner.grant
2016-03-02 14:11:45 -08:00
57370bdf49
first and last on HasTileLinkData
2016-03-02 14:11:39 -08:00
ab30983aa9
Add support for per-way cache metadata
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Exposes new parameter field SplitMetadata to determine whether the metadata array in a particular cache is stored in a single SeqMem or with one SeqMem per way.
Closes #14
2016-03-01 12:19:42 -08:00
6d984273b7
finally fix all release assertions ... hopefully
2016-02-29 15:22:24 -08:00
8873222e42
fix cache release assertion
2016-02-23 16:03:51 -08:00
929d8e31f7
refactor ready/valid logic for routing release messages in the l2
2016-02-19 16:30:26 -08:00
4ff1aea288
fix more Chisel3 deprecations
2016-01-14 14:55:45 -08:00
a953ff384a
Chisel3 compatibility: use more concrete types
2016-01-12 15:32:14 -08:00
a48237f36d
get rid of the rest of the PutBlock special casing in L2
2015-12-16 20:56:29 -08:00
922b1adc9c
Add optional PLRU replacement to the L2
2015-12-16 10:00:56 -08:00
ddc79674f9
fix some issues with cache request merging
2015-12-15 21:31:02 -08:00
ee6514e4f4
make sure WritebackUnit sends correct probe addresses
2015-11-21 15:55:11 -08:00
04383a31f5
Revert "make sure L2MetadataArray assigns unoccupied way if available"
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This reverts commit 1857f36c1e6f2b2859c724eea6ae3cfb2618f81b.
2015-11-21 10:35:40 -08:00
3c95afebc6
Shift set index for multi-bank configurations
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Prior to this commit, the L2 cache banks used the lower bits of the
block address as the set index. However, the lower bits are also used to
route addresses to different banks. As a result, in multi-bank
configurations, only a fraction of the sets in each bank could be
accessed. This commit fixes that problem by using the bits ahead of the
bank index as the set index, so that all sets in the cache can be
accessed.
2015-11-20 23:24:57 -08:00
24f7b9f472
make sure L2MetadataArray assigns unoccupied way if available
2015-11-19 10:45:54 -08:00
2b977325e3
Make prefetch type available in a_type, issue probeInvalidates for putPrefetches
2015-11-16 23:26:13 -08:00
0290635454
amo_shift_bits -> amo_shift_bytes
2015-11-16 19:07:58 -08:00
64aaf71b06
L2AcquireTracker refactor to support merging Gets and Puts into Prefetches of the correct type.
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Transaction metadata for primary and seconday misses now stored in the secondary miss queue.
Added BuiltInAcquireBuilder factory.
2015-11-16 18:10:09 -08:00
03fa06e6e7
fix prefetch lockup on L2 hit
2015-11-15 12:51:34 -08:00
e12efab423
skip meta_write state if no meta write pending
2015-11-13 13:50:35 -08:00
7e7d688a01
make sure L2 passes no-alloc acquires through to outer memory
2015-11-12 15:40:58 -08:00
7733fbe6a3
make sure no-alloc write still updates data array if there is a cache hit
2015-11-12 11:39:36 -08:00
b59ce5fed4
make sure L2 waits for outer grant before sending grant for write request
2015-11-10 16:06:14 -08:00
e3efc09b5b
remove unnecessary UInt encode/decode on releaseMatches path
2015-11-05 17:20:03 -08:00
3698153535
OHToUInt instead of PriorityEncoder on Acq/RelMatches signals in L2Bank
2015-11-03 14:31:35 -08:00
f8594da1d3
depend on external cde library
2015-10-21 18:17:17 -07:00
d391f97953
Minor refactor of StoreGen/AMOALU. Bugfix for 32b ops in L2's AMOALU.
2015-10-16 19:11:06 -07:00
7fa3eb95e3
refactor tilelink params
2015-10-14 12:13:37 -07:00
66ea39638e
GlobalAddrMap
2015-10-14 00:23:28 -07:00
31be6407ec
Removed all traces of params
2015-10-14 00:23:28 -07:00
3b1da4c57e
Revert "replace remaining uses of Vec.fill"
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This reverts commit b6bb4e42127d1ed42b55ec8b859a4e074b347d47.
2015-09-25 17:06:57 -07:00
d1f2d40a90
replace remaining uses of Vec.fill
2015-09-24 17:50:09 -07:00
24389a5257
Chisel3 compatibility fixes
2015-09-11 15:41:39 -07:00
350d530766
Use Vec.fill, not Vec.apply, for Vec literals
2015-08-27 10:00:43 -07:00
94287fed90
Avoid type-unsafe assignments
2015-08-27 09:57:36 -07:00
05d311c517
Use Vec.apply, not Vec.fill, for type nodes
2015-08-27 09:47:02 -07:00
798ddeb5f5
Chisel3 compatibility: use >>Int instead of >>UInt
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The latter doesn't contract widths anymore.
2015-08-04 13:15:17 -07:00
8f7b390353
UInt-> Bits; avoid mixed UInt/SInt code
2015-07-30 23:49:06 -07:00
c70b495f6d
moved buses to junctions repo
2015-07-29 18:04:30 -07:00
a69c749249
Fix compilation with scala 2.11.6
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We forgot to specify return types on overloaded methods, and a previous
version of the scala compiler failed to flag this as an error.
2015-07-28 16:24:45 -07:00
Andrew Waterman
Howard Mao
Henry Cook
Palmer Dabbelt
Albert Magyar