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Author SHA1 Message Date
Wesley W. Terpstra 2f7081aeaf tilelink2: make mask generation reusable 2016-10-10 11:21:50 -07:00
Wesley W. Terpstra b29d34038e axi4: diplomacy capable AXI4 2016-10-10 11:21:50 -07:00
Wesley W. Terpstra dcb9383568 PositionalMultiQueue: work around vcs Lint report 
Lint-[PCTIO-L] Ports coerced to inout
rocket-chip/vsim/generated-src/unittest.UncoreUnitTestConfig.v, 127524
"io_deq_0_valid"
  Port "io_deq_0_valid" declared as output in module "PositionalMultiQueue_16"
  may need to be inout. Coercing to inout.
 2016-10-10 11:21:49 -07:00
Wesley W. Terpstra 5d905a5310 PositionalMultiQueue: shared storage FIFO 1-push n-pop 2016-10-10 11:21:49 -07:00
Wesley W. TerpstraandMegan Wachs e5ac0f717f tilelink2: split isolation gates by direction 2016-10-07 12:03:43 -07:00
Wesley W. TerpstraandGitHub 6ec2e7c5bd tilelink2: Legacy should preserve the access size (#378) 
* tilelink2: Legacy should preserve the access size
* Legacy: extract missing size information for TL1 Puts
 2016-10-03 17:25:31 -07:00
Wesley W. TerpstraandGitHub 72e8c6f589 Merge pull request #379 from ucb-bar/axi-prefactor 
Axi prefactor
 2016-10-03 16:49:37 -07:00
Wesley W. Terpstra f05298d9bc tilelink2: move general-purpose code out of tilelink2 package 2016-10-03 16:22:28 -07:00
Wesley W. Terpstra c85e42a303 tilelink2: Nodes should accept full PortParameters 
We need this for terminal clients/managers that bridge multiple
non-TL2 devices.
 2016-10-03 16:09:49 -07:00
Wesley W. TerpstraandYunsup Lee f2ca2178bf graphML: CTO's like colour 2016-10-03 15:05:45 -07:00
Wesley W. TerpstraandYunsup Lee fe0875b084 LazyModule: output final verilog Module name 2016-10-03 15:05:45 -07:00
Wesley W. TerpstraandYunsup Lee 0a4ef66894 BaseTop: record top module; more general than GraphML 2016-10-03 15:05:45 -07:00
Wesley W. TerpstraandAndrew Waterman 52c1a053ff tilelink2 RegisterRouter: test fully Decoupled behaviour 2016-10-02 02:24:02 -07:00
Wesley W. TerpstraandAndrew Waterman 422e6357a4 tilelink2 RegisterCrossing: Queues go from RV to Irrevocable 
AsyncQueue is still a Queue.
 2016-10-02 02:24:02 -07:00
Wesley W. TerpstraandAndrew Waterman 02f89fb530 RegMapper: clarify interface is DecoupledIO 2016-10-02 02:24:02 -07:00
Wesley W. TerpstraandAndrew Waterman 8a268268ad tilelink2 RegField: clarify restrictions on functions 
RegMapper is fundamentaly DecoupledIO.
Let the user take advantage of this.
Clarify that rules on data handling.
 2016-10-02 02:24:02 -07:00
Wesley W. TerpstraandAndrew Waterman bff0ffa428 tilelink2 RegisterRouter: fix output data glitches 
If a device changes a register while it's being read but not yet accepted,
this an lead to 'data' changing while 'valid' is high. A violation. The
problem is that RegMapper is fundamentally DecoupledIO. So fix it with a
Queue.
 2016-10-02 02:24:02 -07:00
Wesley W. TerpstraandGitHub 0ebab0976a tilelink2 Isolation: add enable signal (#368) 2016-09-30 04:54:40 -07:00
Wesley W. TerpstraandGitHub 891a253bee Merge pull request #367 from ucb-bar/tl2-isolation 
Tl2 isolation
 2016-09-30 02:19:44 -07:00
Wesley W. Terpstra d3547a6193 tilelink2: Isolation gate insertion module 2016-09-30 01:50:33 -07:00
Wesley W. Terpstra 9b0654be52 tilelink2 Crossing: helpful constructor objects 2016-09-30 01:48:47 -07:00
Wesley W. Terpstra 80f7bb49e3 tilelink2: helper objects operate on OutwardNodes 2016-09-30 01:39:35 -07:00
Wesley W. TerpstraandGitHub 8730887baa Merge pull request #364 from ucb-bar/tl2-async-nodes 
Tl2 async nodes
 2016-09-29 18:18:31 -07:00
Wesley W. Terpstra 6d8c965f04 tilelink2 Crossing: cut the crossing between clock domains 2016-09-29 17:35:10 -07:00
Wesley W. Terpstra 20f42a8762 tilelink2: reuse the halves of the AsyncQueue 2016-09-29 17:35:08 -07:00
Wesley W. Terpstra 8e4c1e567c tilelink2: add types for a TL clockless interface 2016-09-29 17:33:11 -07:00
Wesley W. Terpstra 02ce8c2ca4 tilelink2 Nodes: rename RootNode => BaseNode 2016-09-29 17:33:11 -07:00
Wesley W. Terpstra 754fcf9831 tilelink2: rename BaseNode to SimpleNode 2016-09-29 17:33:11 -07:00
Wesley W. Terpstra cfdb8ca797 tilelink2 LazyModule: remove obsolete connect method 2016-09-29 17:33:11 -07:00
Wesley W. Terpstra f2e438833c tilelink2 Nodes: generalize a node into inner and outer halves 
This lets us create nodes which transform from one bus to another.
 2016-09-29 17:33:11 -07:00
Wesley W. TerpstraandHenry Cook 3926cb936b rocketchip: add pbus width and AMO With classes (#357) 2016-09-27 15:52:13 -07:00
Wesley W. TerpstraandAndrew Waterman eaea138d0d tilelink2: don't use chisel3 namespace (#355) 2016-09-27 14:44:26 -07:00
Wesley W. TerpstraandHenry Cook 357d06ac9c tilelink2 WidthWidget: Gets must have their mask adjusted (#353) 
The mask of a Get should also be converted.

This manifested as a bug when going from 32=>64 bits. A large Get
could end up with mask that was not full.
 2016-09-27 14:06:02 -07:00
Wesley W. TerpstraandGitHub d9e209365d Tl2 addr width0 (#346) 
* tilelink2 Edges: add accessor methods for address and addr_{hi,lo}

* tilelink2: use addr_lo instead of relying on truncation

Truncation can mess up if the width should be 0, but IS 1.
 2016-09-26 17:00:03 -07:00
Wesley W. TerpstraandGitHub 72c205b54f tilelink2 AddressSet: add .misaligned(low, size) helper method (#345) 
This helps devices with misaligned ranges still connect to TL2.
 2016-09-26 16:01:09 -07:00
Wesley W. TerpstraandYunsup Lee dd9558f45d rocketchip: generate GraphML output 2016-09-26 14:35:46 -07:00
Wesley W. TerpstraandYunsup Lee 1773eb4405 tilelink2 LazyModule: output GraphML of the bus 2016-09-26 14:35:46 -07:00
Wesley W. TerpstraandYunsup Lee 35da9320bc tilelink2 Nodes: expose connectivity in RootNode 2016-09-26 14:35:46 -07:00
Wesley W. TerpstraandGitHub 14cd39e045 rocketchip: rename identically names devices with _%d (#340) 
* rocketchip: rename identically names devices with _%d

If you connect two devices with the same name in TL2 (totally ok there),
when they get put into the TL1 addrmap, one gets silently overwritten.
This renames the second occurance as _1, third as _2, and so on...

* junctions: blow if duplicates add to addrmap
 2016-09-26 13:05:49 -07:00
Wesley W. TerpstraandGitHub d787bae0d0 tilelink2 Xbar: decouple ready from valid (#338) 
This moves the Xbar from using custom code to using the Arbiter.
The arbiter has better ready-valid decoupling.
 2016-09-23 16:24:29 -07:00
Wesley W. TerpstraandYunsup Lee d175bb314d Periphery: make bus width and arithmetic atomics configurable (#337) 2016-09-23 15:25:58 -07:00
Wesley W. TerpstraandGitHub 47843d8ec1 tilelink2: maxLgSize should be accurate (#332) 2016-09-22 22:06:22 -07:00
Wesley W. TerpstraandGitHub 7ee79efc15 Merge pull request #333 from ucb-bar/tl2-api-changes 
Tl2 api changes
 2016-09-22 21:20:27 -07:00
Wesley W. Terpstra c5706afc11 RegField: remove obsolete split method 
This is now natively supported by the regmap(...) invocation.
 2016-09-22 20:52:47 -07:00
Wesley W. Terpstra fc44151f10 RegField: add name and description fields 
In the future we can generate interesting documentation and headers.
 2016-09-22 20:52:46 -07:00
Wesley W. Terpstra 5e34b313ee RegMapper: regmap(...) now takes BYTE addresses 
If a device has configurable bus-width, we need a stable way of
enumerating registers. The byte offset stays unchanged.

This change also makes it possible to put an arbitrary number of RegFields
starting at some address which are then chopped up into appropriately bus-
sized registers.
 2016-09-22 20:52:46 -07:00
Wesley W. Terpstra 972ca06729 RegField: remove RegField.bytes; it was dangerous 
The implementation unconditionally drove the register.
This made it incompatible with drivers from the device itself.
Besides, writing only parts of a register at a time is ultra-shady.
 2016-09-22 20:52:46 -07:00
Wesley W. Terpstra a421469754 tilelink2: change adapters to use TLAdapter(params, defaults)(node) 
This API makes it much more readable when you have multiple adapters
combined into a single line. The arguments for each adapter stay
beside the adapter.

For example, this:
  peripheryBus.node := TLWidthWidget(TLBuffer(TLAtomicAutomata()(TLHintHandler(legacy.node))), legacy.tlDataBytes)
becomes this:
  peripheryBus.node := TLWidthWidget(legacy.tlDataBytes)(TLBuffer()(TLAtomicAutomata()(TLHintHandler()(legacy.node))))
 2016-09-22 20:52:46 -07:00
Wesley W. Terpstra a3e88fa13a tilelink2 Atomics: optimize the sign-extension circuit 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra 9f1f6fc61f Comparator: tolerate mismatched data when it is undefined 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra ed038678ef tilelink2 Fuzzer: work around for firrtl/verilator performance issue 
Big Vec()s cause very slow compilation.
 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra 1e7480b6fc tilelink2 Monitor: work around for firrtl/verilator performance issue 
Big Vec()s cause problems for these tools.
 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra ec2030df31 tilelink2 Legacy: convert TL1 atomic operand size 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra 0a3718881f rocketchip: re-enable testing of atomics 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra e5da3eb8bb tilelink2 Atomics: support arithmetic atomics 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra 5b80fe5b51 tilelink2 Atomics: support Logical AMOs 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra 4066fbe18f tilelink2 RAMModel: exploit latency to remove bypass 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra e0ade8c5a9 tilelink2 Atomics: exploit minLatency to eliminate bypass 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra 3bb2580223 tilelink2 Monitor: detect minLatency violations 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra 2b24c4b1b4 tilelink2: most adapters can wipe away latency 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra c115913624 tilelink2 Buffer: increase the minLatency on ports 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra 05beb20dc4 tilelink2: specify the minLatency for SRAM+RR 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra 44277c1db3 tilelink2 Parameters: include a minLatency parameter for optimization 2016-09-22 15:18:54 -07:00
Wesley W. Terpstra cf39c32b0e tilelink2 Fuzzer: test Atomics 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra 2b9403633d tilelink2 RAMModel: support (by ignoring) atomics 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra ce204f604a tilelink2 AtomicAutomata: prototype flow control complete 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra 42b10356fa tilelink2: add a general-purpose Arbiter 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra 7636e772c8 tilelink2 Fuzzer: only generate legal atomics 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra f5d604d8f8 tilelink2 Parameters: poison ports with unsafe atomics 
We need to detect if an AtomicAutomata's output ever gets mixed
with some other source of operations.
 2016-09-22 15:18:53 -07:00
Wesley W. Terpstra d1151e2f0f tilelink2 Nodes: split connect into eager and lazy halves 2016-09-22 15:18:50 -07:00
Wesley W. Terpstra 684072023f tilelink2 Monitor: make it a LazyModule in the hierarchy 2016-09-22 15:14:20 -07:00
Wesley W. Terpstra def497861b tilelink2 Bundles: add 1-way snoop bundles 2016-09-22 15:14:20 -07:00
Wesley W. Terpstra 69a1f8cd1f tilelink2 Monitor: detect if sources are mishandled 2016-09-22 15:14:19 -07:00
Wesley W. TerpstraandGitHub 3f3defb130 Merge pull request #329 from ucb-bar/fragmenter 
tilelink2 Fragmenter: Mask low bits of D channel addr_lo
 2016-09-22 14:42:55 -07:00
Wesley W. TerpstraandGitHub aa956c0108 Merge pull request #312 from ucb-bar/tl2-cheap-address-decode 
Tl2 cheap address decode
 2016-09-17 17:37:03 -07:00
Wesley W. Terpstra 9817a00ed9 tilelink2: Fuzzer should check address validity before injection 2016-09-17 17:07:21 -07:00
Wesley W. Terpstra b11839f5a1 tilelink2: differentiate fast/safe address lookup cases 2016-09-17 17:04:18 -07:00
Wesley W. Terpstra b4baae4214 tilelink2: minimize Xbar decode logic 2016-09-17 16:14:25 -07:00
Wesley W. Terpstra 76d8ed6a69 tilelink2: remove 'strided'; !contiguous is clearer 2016-09-17 16:14:25 -07:00
Wesley W. Terpstra fa0f119f3c tilelink2: consider the implications of negative address mask 2016-09-17 16:14:22 -07:00
Wesley W. Terpstra e437508548 tilelink2: track interrupt connectivity like in TL2 2016-09-17 14:43:48 -07:00
Wesley W. TerpstraandGitHub fd3ac4653c Merge pull request #311 from ucb-bar/rom-executable 
Rom executable
 2016-09-17 01:28:52 -07:00
Wesley W. Terpstra 01c1886b9d Utils: cacheable only if there is a cache manager 2016-09-17 00:56:21 -07:00
Wesley W. Terpstra 6c3269a1d8 SRAM: optionally (default: true) executable 2016-09-17 00:19:37 -07:00
Wesley W. Terpstra e749558190 ROM: optionally (default: true) executable 2016-09-17 00:19:09 -07:00
Wesley W. Terpstra c70045b8b3 Utils: express cacheability from TL2 to TL1 2016-09-17 00:16:40 -07:00
Wesley W. Terpstra e3d2bd3323 Top: print memory region properties, RWX [C] 2016-09-17 00:16:00 -07:00
Wesley W. TerpstraandGitHub 75c73fce37 Merge pull request #309 from ucb-bar/tl2-addrmap 
Tl2 addrmap
 2016-09-16 19:09:22 -07:00
Wesley W. Terpstra 5c858685aa Utils: support managers with multiple addresses 2016-09-16 18:03:49 -07:00
Wesley W. Terpstra a9382b3116 Periphery: test bench looks for "testram" 2016-09-16 17:47:20 -07:00
Wesley W. Terpstra b5ce6150c7 Periphery: dynamically create address map + config string for TL2 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra 8876d83640 Prci: preserve Andrew's preferred clint name 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra a357c1d42e tilelink2: create DTS for devices automagically 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra 2587234838 tilelink2 TLNodes: capture nodePath in {Client,Manager}Parameters 2016-09-16 17:28:47 -07:00
Wesley W. Terpstra 915a929af1 tilelink2: Nodes can now mix context into parameters 2016-09-16 17:28:47 -07:00
Wesley W. TerpstraandGitHub 503ce14c98 Merge pull request #307 from ucb-bar/address-shrink 
RR: undefined regs return zeros
 2016-09-16 16:55:35 -07:00
Wesley W. Terpstra dae0918c85 tilelink2 RegisterRouter: support undefZero 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra f0f553f227 tilelink2 RegisterRouterTest: work around firrtl warning 
Using io.wready leads to verilog that reads from the output...

Lint-[PCTIO-L] Ports coerced to inout
/scratch/terpstra/federation/rocket-chip/vsim/generated-src/UnitTestHarness.UnitTestConfig.v, 24860
"io_wready"
  Port "io_wready" declared as output in module "RRTestCombinational_29" may
  need to be inout. Coercing to inout.
 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra 3fcc1a4460 tilelink2 RegisterRouterTest: don't couple fire into helpers 2016-09-16 16:09:00 -07:00
Wesley W. Terpstra 2210e71f42 tilelink2 AddressDecoder: validate output of optimization 2016-09-16 16:09:00 -07:00