tilelink2 AtomicAutomata: prototype flow control complete
This commit is contained in:
Wesley W. Terpstra
249
src/main/scala/uncore/tilelink2/AtomicAutomata.scala
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249
src/main/scala/uncore/tilelink2/AtomicAutomata.scala
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// See LICENSE for license details.
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package uncore.tilelink2
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import Chisel._
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import chisel3.internal.sourceinfo.SourceInfo
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import scala.math.{min,max}
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// Ensures that all downstream RW managers support Atomic operationss.
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// If !passthrough, intercept all Atomics. Otherwise, only intercept those unsupported downstream.
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class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true) extends LazyModule
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{
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require (concurrency >= 1)
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val node = TLAdapterNode(
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clientFn = { case Seq(cp) => require (!cp.unsafeAtomics); cp.copy(unsafeAtomics = true) },
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managerFn = { case Seq(mp) => mp.copy(managers = mp.managers.map { m =>
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val ourSupport = TransferSizes(1, mp.beatBytes)
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def widen(x: TransferSizes) = if (passthrough && x.min <= 2*mp.beatBytes) TransferSizes(1, max(mp.beatBytes, x.max)) else ourSupport
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val canDoit = m.supportsPutFull.contains(ourSupport) && m.supportsGet.contains(ourSupport)
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// Blow up if there are devices to which we cannot add Atomics, because their R|W are too inflexible
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require (!m.supportsPutFull || !m.supportsGet || canDoit)
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m.copy(
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supportsArithmetic = if (!arithmetic || !canDoit) m.supportsArithmetic else widen(m.supportsArithmetic),
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supportsLogical = if (!logical || !canDoit) m.supportsLogical else widen(m.supportsLogical))
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})})
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lazy val module = new LazyModuleImp(this) {
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val io = new Bundle {
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val in = node.bundleIn
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val out = node.bundleOut
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}
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val in = io.in(0)
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val out = io.out(0)
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val edgeIn = node.edgesIn(0)
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val edgeOut = node.edgesOut(0)
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val managers = edgeOut.manager.managers
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// To which managers are we adding atomic support?
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val ourSupport = TransferSizes(1, edgeOut.manager.beatBytes)
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val managersNeedingHelp = managers.filter { m =>
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m.supportsPutFull.contains(ourSupport) &&
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m.supportsGet.contains(ourSupport) &&
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((logical && !m.supportsLogical .contains(ourSupport)) ||
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(arithmetic && !m.supportsArithmetic.contains(ourSupport)) ||
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!passthrough) // we will do atomics for everyone we can
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}
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// We cannot add atomcis to a non-FIFO manager
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managersNeedingHelp foreach { m => require (m.fifoId.isDefined) }
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// We need to preserve FIFO semantics across FIFO domains, not managers
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// Suppose you have Put(42) Atomic(+1) both inflight; valid results: 42 or 43
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// If we allow Put(42) Get() Put(+1) concurrent; valid results: 42 43 OR undef
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// Making non-FIFO work requires waiting for all Acks to come back (=> use FIFOFixer)
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val domainsNeedingHelp = managersNeedingHelp.map(_.fifoId.get).distinct
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// Don't overprovision the CAM
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val camSize = min(domainsNeedingHelp.size, concurrency)
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// Compact the fifoIds to only those we care about
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val camFifoIds = managers.map(m => UInt(m.fifoId.map(id => max(0, domainsNeedingHelp.indexOf(id))).getOrElse(0)))
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// CAM entry state machine
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val FREE = UInt(0) // unused waiting on Atomic from A
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val GET = UInt(3) // Get sent down A waiting on AccessDataAck from D
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val AMO = UInt(2) // AccessDataAck sent up D waiting for A availability
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val ACK = UInt(1) // Put sent down A waiting for PutAck from D
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class CAMEntry extends Bundle {
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val state = UInt(width = 2)
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val fifoId = UInt(width = log2Up(domainsNeedingHelp.size))
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val bits = new TLBundleA(in.a.bits.params)
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}
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def helper(select: Seq[Bool], x: Seq[TransferSizes], lgSize: UInt) =
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if (!passthrough) Bool(false) else
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if (x.map(_ == x(0)).reduce(_ && _)) x(0).containsLg(lgSize) else
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Mux1H(select, x.map(_.containsLg(lgSize)))
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// Do we need to do anything at all?
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if (camSize > 0) {
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class CAM_S extends Bundle {
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val state = UInt(width = 2)
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}
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class CAM_A extends Bundle {
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val bits = new TLBundleA(out.a.bits.params)
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val fifoId = UInt(width = log2Up(domainsNeedingHelp.size))
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}
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class CAM_D extends Bundle {
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val data = UInt(width = out.a.bits.params.dataBits)
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}
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val initval = Wire(new CAM_S)
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initval.state := FREE
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val cam_s = RegInit(Vec.fill(camSize)(initval))
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val cam_a = Reg(Vec(camSize, new CAM_A))
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val cam_d = Reg(Vec(camSize, new CAM_D))
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val cam_free = cam_s.map(_.state === FREE)
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val cam_amo = cam_s.map(_.state === AMO)
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val cam_abusy = cam_s.map(e => e.state === GET || e.state === AMO) // A is blocked
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val cam_dmatch = cam_s.map(e => e.state === GET || e.state === ACK) // D should inspect these entries
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// Can the manager already handle this message?
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val a_size = edgeIn.size(in.a.bits)
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val a_select = edgeOut.manager.findFast(edgeIn.address(in.a.bits))
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val a_canLogical = helper(a_select, managers.map(_.supportsLogical), a_size)
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val a_canArithmetic = helper(a_select, managers.map(_.supportsArithmetic), a_size)
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val a_isLogical = in.a.bits.opcode === TLMessages.LogicalData
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val a_isArithmetic = in.a.bits.opcode === TLMessages.ArithmeticData
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val a_isSupported = Mux(a_isLogical, a_canLogical, Mux(a_isArithmetic, a_canArithmetic, Bool(true)))
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// Must we do a Put?
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val a_cam_any_put = cam_amo.reduce(_ || _)
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val a_cam_por_put = cam_amo.scanLeft(Bool(false))(_||_).init
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val a_cam_sel_put = (cam_amo zip a_cam_por_put) map { case (a, b) => a && !b }
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val a_cam_adata = PriorityMux(cam_amo, cam_a.map(_.bits))
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val a_cam_ddata = PriorityMux(cam_amo, cam_d.map(_.data))
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// Does the A request conflict with an inflight AMO?
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val a_fifoId = Mux1H(a_select, camFifoIds)
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val a_cam_busy = (cam_abusy zip cam_a.map(_.fifoId === a_fifoId)) map { case (a,b) => a&&b } reduce (_||_)
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// (Where) are we are allocating in the CAM?
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val a_cam_any_free = cam_free.reduce(_ || _)
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val a_cam_por_free = cam_free.scanLeft(Bool(false))(_||_).init
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val a_cam_sel_free = (cam_free zip a_cam_por_free) map { case (a,b) => a && !b }
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// !!! perform the AMO op
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val amo_data = a_cam_adata.data + a_cam_ddata
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// Potentially mutate the message from inner
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val source_i = Wire(in.a)
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val a_allow = !a_cam_busy && (a_isSupported || a_cam_any_free)
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in.a.ready := source_i.ready && a_allow
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source_i.valid := in.a.valid && a_allow
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source_i.bits := in.a.bits
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when (!a_isSupported) { // minimal mux difference
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source_i.bits.opcode := TLMessages.Get
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source_i.bits.param := UInt(0)
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}
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// Potentially take the message from the CAM
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val source_c = Wire(in.a)
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source_c.valid := a_cam_any_put
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source_c.bits := edgeOut.Put(a_cam_adata.source, edgeIn.address(a_cam_adata), a_cam_adata.size, amo_data)._2
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// Finishing an AMO from the CAM has highest priority
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TLArbiter(TLArbiter.lowestIndexFirst)(out.a, (UInt(1), source_c), (edgeOut.numBeats(in.a.bits), source_i))
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// Capture the A state into the CAM
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when (source_i.fire() && !a_isSupported) {
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(a_cam_sel_free zip cam_a) foreach { case (en, r) =>
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when (en) {
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r.fifoId := a_fifoId
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r.bits := in.a.bits
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}
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}
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(a_cam_sel_free zip cam_s) foreach { case (en, r) =>
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when (en) {
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r.state := GET
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}
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}
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}
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// Advance the put state
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when (source_c.fire()) {
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(a_cam_sel_put zip cam_s) foreach { case (en, r) =>
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when (en) {
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r.state := ACK
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}
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}
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}
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// We need to deal with a potential D response in the same cycle as the A request
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val d_cam_sel_raw = cam_a.map(_.bits.source === in.d.bits.source)
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val d_cam_sel_match = (d_cam_sel_raw zip cam_dmatch) map { case (a,b) => a&&b }
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val d_cam_data = Mux1H(d_cam_sel_match, cam_d.map(_.data))
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val d_cam_sel_bypass = out.d.bits.source === in.a.bits.source && in.a.valid && out.d.valid && !a_isSupported
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val d_cam_sel = (a_cam_sel_free zip d_cam_sel_match) map { case (a,d) => Mux(d_cam_sel_bypass, a, d) }
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val d_cam_sel_any = d_cam_sel_bypass || d_cam_sel_match.reduce(_ || _)
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val d_ackd = out.d.bits.opcode === TLMessages.AccessAckData
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val d_ack = out.d.bits.opcode === TLMessages.AccessAck
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when (out.d.fire()) {
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(d_cam_sel zip cam_d) foreach { case (en, r) =>
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when (en && d_ackd) {
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r.data := out.d.bits.data
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}
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}
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(d_cam_sel zip cam_s) foreach { case (en, r) =>
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when (en) {
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// Note: it is important that this comes AFTER the := GET, so we can go FREE=>GET=>AMO in one cycle
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r.state := Mux(d_ackd, AMO, FREE)
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}
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}
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}
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val d_drop = d_ackd && d_cam_sel_any
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val d_replace = d_ack && d_cam_sel_match.reduce(_ || _)
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in.d.valid := out.d.valid && !d_drop
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out.d.ready := in.d.ready || d_drop
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in.d.bits := out.d.bits
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when (d_replace) { // minimal muxes
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in.d.bits.opcode := TLMessages.AccessAckData
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in.d.bits.data := d_cam_data
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}
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} else {
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out.a.valid := in.a.valid
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in.a.ready := out.a.ready
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out.a.bits := in.a.bits
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in.d.valid := out.d.valid
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out.d.ready := in.d.ready
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in.d.bits := out.d.bits
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}
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if (edgeOut.manager.anySupportAcquire && edgeIn.client.anySupportProbe) {
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in.b.valid := out.b.valid
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out.b.ready := in.b.ready
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in.b.bits := out.b.bits
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out.c.valid := in.c.valid
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in.c.ready := out.c.ready
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out.c.bits := in.c.bits
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out.e.valid := in.e.valid
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in.e.ready := out.e.ready
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out.e.bits := in.e.bits
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} else {
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in.b.valid := Bool(false)
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in.c.ready := Bool(true)
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in.e.ready := Bool(true)
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out.b.ready := Bool(true)
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out.c.valid := Bool(false)
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out.e.valid := Bool(false)
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}
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}
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}
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object TLAtomicAutomata
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{
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// applied to the TL source node; y.node := TLAtomicAutomata(x.node)
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def apply(logical: Boolean = true, arithmetic: Boolean = true, concurrency: Int = 1, passthrough: Boolean = true)(x: TLBaseNode)(implicit sourceInfo: SourceInfo): TLBaseNode = {
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val atomics = LazyModule(new TLAtomicAutomata(logical, arithmetic, concurrency, passthrough))
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atomics.node := x
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atomics.node
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}
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}
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