RegMapper: regmap(...) now takes BYTE addresses
If a device has configurable bus-width, we need a stable way of enumerating registers. The byte offset stays unchanged. This change also makes it possible to put an arbitrary number of RegFields starting at some address which are then chopped up into appropriately bus- sized registers.
This commit is contained in:
Wesley W. Terpstra
parent
972ca06729
commit
5e34b313ee
@ -74,14 +74,11 @@ trait CoreplexLocalInterrupterModule extends Module with HasRegMap with MixCorep
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* bff8 mtime lo
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* bffc mtime hi
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*/
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val ipi_base = 0
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val timecmp_base = c.timecmpOffset(0) / c.beatBytes
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val time_base = c.timeOffset / c.beatBytes
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regmap((
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RegField.split(makeRegFields(ipi), ipi_base, c.beatBytes) ++
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RegField.split(makeRegFields(timecmp.flatten), timecmp_base, c.beatBytes) ++
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RegField.split(makeRegFields(time), time_base, c.beatBytes)):_*)
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regmap(
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0 -> makeRegFields(ipi),
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c.timecmpOffset(0) -> makeRegFields(timecmp.flatten),
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c.timeOffset -> makeRegFields(time))
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def makeRegFields(s: Seq[UInt]) = s.map(r => RegField(regWidth, r))
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}
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@ -27,7 +27,7 @@ trait ExampleModule extends HasRegMap
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regmap(
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0 -> Seq(
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RegField(params.num, state)),
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1 -> Seq(
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4 -> Seq(
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RegField.w1ToClear(4, pending, state)))
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}
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@ -85,7 +85,9 @@ case class RegField(width: Int, read: RegReadFn, write: RegWriteFn)
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object RegField
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{
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// Byte address => sequence of bitfields, lowest index => lowest address
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type Map = (Int, Seq[RegField])
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def apply(n: Int) : RegField = apply(n, (), ())
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def apply(n: Int, rw: UInt) : RegField = apply(n, rw, rw)
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def r(n: Int, r: RegReadFn) : RegField = apply(n, r, ())
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@ -29,26 +29,35 @@ object RegMapper
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{
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// Create a generic register-based device
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def apply(bytes: Int, concurrency: Int, undefZero: Boolean, in: DecoupledIO[RegMapperInput], mapping: RegField.Map*) = {
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val regmap = mapping.toList.filter(!_._2.isEmpty)
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require (!regmap.isEmpty)
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// Ensure no register appears twice
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regmap.combinations(2).foreach { case Seq((reg1, _), (reg2, _)) =>
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require (reg1 != reg2)
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}
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val bytemap = mapping.toList
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// Don't be an asshole...
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regmap.foreach { reg => require (reg._1 >= 0) }
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bytemap.foreach { byte => require (byte._1 >= 0) }
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// Transform all fields into bit offsets Seq[(bit, field)]
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val bitmap = bytemap.map { case (byte, fields) =>
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val bits = fields.scanLeft(byte * 8)(_ + _.width).init
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bits zip fields
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}.flatten.sortBy(_._1)
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// Detect overlaps
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(bitmap.init zip bitmap.tail) foreach { case ((lbit, lfield), (rbit, rfield)) =>
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require (lbit + lfield.width <= rbit, s"Register map overlaps at bit ${rbit}.")
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}
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// Group those fields into bus words Map[word, List[(bit, field)]]
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val wordmap = bitmap.groupBy(_._1 / (8*bytes))
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// Make sure registers fit
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val inParams = in.bits.params
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val inBits = inParams.indexBits
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assert (regmap.map(_._1).max < (1 << inBits))
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assert (wordmap.keySet.max < (1 << inBits), "Register map does not fit in device")
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val out = Wire(Irrevocable(new RegMapperOutput(inParams)))
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val front = Wire(Irrevocable(new RegMapperInput(inParams)))
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front.bits := in.bits
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// Must this device pipeline the control channel?
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val pipelined = regmap.map(_._2.map(_.pipelined)).flatten.reduce(_ || _)
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val pipelined = wordmap.values.map(_.map(_._2.pipelined)).flatten.reduce(_ || _)
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val depth = concurrency
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require (depth >= 0)
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require (!pipelined || depth > 0, "Register-based device with request/response handshaking needs concurrency > 0")
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@ -60,7 +69,7 @@ object RegMapper
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def ofBits(bits: List[Boolean]) = bits.foldRight(0){ case (x,y) => (if (x) 1 else 0) | y << 1 }
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// Find the minimal mask that can decide the register map
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val mask = AddressDecoder(regmap.map(_._1))
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val mask = AddressDecoder(wordmap.keySet.toList)
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val maskMatch = ~UInt(mask, width = inBits)
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val maskFilter = toBits(mask)
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val maskBits = maskFilter.filter(x => x).size
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@ -75,17 +84,22 @@ object RegMapper
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val iRightReg = Array.fill(regSize) { Bool(true) }
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val oRightReg = Array.fill(regSize) { Bool(true) }
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// Flatten the regmap into (RegIndex:Int, Offset:Int, field:RegField)
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val flat = regmap.map { case (reg, fields) =>
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val offsets = fields.scanLeft(0)(_ + _.width).init
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val index = regIndexI(reg)
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val uint = UInt(reg, width = inBits)
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// Transform the wordmap into minimal decoded indexes, Seq[(index, bit, field)]
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val flat = wordmap.toList.map { case (word, fields) =>
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val index = regIndexI(word)
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val uint = UInt(word, width = inBits)
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if (undefZero) {
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iRightReg(index) = ((front.bits.index ^ uint) & maskMatch) === UInt(0)
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oRightReg(index) = ((back .bits.index ^ uint) & maskMatch) === UInt(0)
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}
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// println("mapping 0x%x -> 0x%x for 0x%x/%d".format(reg, index, mask, maskBits))
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(offsets zip fields) map { case (o, f) => (index, o, f) }
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// Confirm that no field spans a word boundary
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fields foreach { case (bit, field) =>
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val off = bit - 8*bytes*word
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// println(s"Reg ${word}: [${off}, ${off+field.width})")
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require (off + field.width <= bytes * 8, s"Field at word ${word}*(${bytes}B) has bits [${off}, ${off+field.width}), which exceeds word limit.")
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}
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// println("mapping 0x%x -> 0x%x for 0x%x/%d".format(word, index, mask, maskBits))
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fields.map { case (bit, field) => (index, bit-8*bytes*word, field) }
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}.flatten
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// Forward declaration of all flow control signals
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@ -183,14 +183,14 @@ object RRTest0Map
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// All fields must respect byte alignment, or else it won't behave like an SRAM
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val map = Seq(
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0 -> Seq(aa(8), ar(8), ad(8), ae(8)),
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1 -> Seq(ra(8), rr(8), rd(8), re(8)),
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2 -> Seq(da(8), dr(8), dd(8), de(8)),
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3 -> Seq(ea(8), er(8), ed(8), ee(8)),
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4 -> Seq(aa(3), ar(5), ad(1), ae(7), ra(2), rr(6), rd(4), re(4)),
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5 -> Seq(da(3), dr(5), dd(1), de(7), ea(2), er(6), ed(4), ee(4)),
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6 -> Seq(aa(8), rr(8), dd(8), ee(8)),
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7 -> Seq(ar(8), rd(8), de(8), ea(8)))
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0 -> Seq(aa(8), ar(8), ad(8), ae(8)),
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4 -> Seq(ra(8), rr(8), rd(8), re(8)),
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8 -> Seq(da(8), dr(8), dd(8), de(8)),
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12 -> Seq(ea(8), er(8), ed(8), ee(8)),
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16 -> Seq(aa(3), ar(5), ad(1), ae(7), ra(2), rr(6), rd(4), re(4)),
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20 -> Seq(da(3), dr(5), dd(1), de(7), ea(2), er(6), ed(4), ee(4)),
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24 -> Seq(aa(8), rr(8), dd(8), ee(8)),
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28 -> Seq(ar(8), rd(8), de(8), ea(8)))
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}
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object RRTest1Map
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@ -203,8 +203,8 @@ object RRTest1Map
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def bb(bits: Int) = request(bits, busy, busy)
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val map = RRTest0Map.map.take(6) ++ Seq(
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6 -> Seq(pp(8), pb(8), bp(8), bb(8)),
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7 -> Seq(pp(3), pb(5), bp(1), bb(7), pb(5), bp(3), pp(4), bb(4)))
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24 -> Seq(pp(8), pb(8), bp(8), bb(8)),
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28 -> Seq(pp(3), pb(5), bp(1), bb(7), pb(5), bp(3), pp(4), bb(4)))
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}
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trait RRTest0Bundle
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