riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tilelink2 Monitor: detect minLatency violations

Browse Source
This commit is contained in:
Wesley W. Terpstra 2016-09-21 18:06:39 -07:00
parent 2b24c4b1b4
commit 3bb2580223
1 changed files with 4 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/main/scala/uncore/tilelink2/Monitor.scala
View File

@ -438,6 +438,10 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source
val a_bypass = bypass && bundle.d.valid && d_last
val d_bypass = bypass && bundle.a.valid && a_last
if (edge.manager.minLatency > 0) {
assert(!bypass || !bundle.a.valid || !bundle.d.valid, s"'A' and 'D' concurrent, despite minlatency ${edge.manager.minLatency}" + extra)
}
when (bundle.a.fire()) {
a_counter := Mux(a_first, a_beats1, a_counter - UInt(1))
when (a_last) { inflight(bundle.a.bits.source) := Bool(true) }