tilelink2 Nodes: generalize a node into inner and outer halves
This lets us create nodes which transform from one bus to another.
This commit is contained in:
Wesley W. Terpstra
parent
ceb9c53c7d
commit
f2e438833c
@ -23,13 +23,13 @@ object IntRange
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case class IntSourceParameters(
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range: IntRange,
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nodePath: Seq[IntBaseNode] = Seq())
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nodePath: Seq[RootNode] = Seq())
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{
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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}
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case class IntSinkParameters(
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nodePath: Seq[IntBaseNode] = Seq())
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nodePath: Seq[RootNode] = Seq())
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{
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val name = nodePath.lastOption.map(_.lazyModule.name).getOrElse("disconnected")
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}
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@ -49,8 +49,8 @@ case class IntEdge(source: IntSourcePortParameters, sink: IntSinkPortParameters)
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object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, IntEdge, IntEdge, Vec[Bool]]
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{
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def edgeO(po: IntSourcePortParameters, pi: IntSinkPortParameters): IntEdge = IntEdge(po, pi)
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def edgeI(po: IntSourcePortParameters, pi: IntSinkPortParameters): IntEdge = IntEdge(po, pi)
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def edgeO(pd: IntSourcePortParameters, pu: IntSinkPortParameters): IntEdge = IntEdge(pd, pu)
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def edgeI(pd: IntSourcePortParameters, pu: IntSinkPortParameters): IntEdge = IntEdge(pd, pu)
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def bundleO(eo: Seq[IntEdge]): Vec[Vec[Bool]] = {
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if (eo.isEmpty) Vec(0, Vec(0, Bool())) else
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Vec(eo.size, Vec(eo.map(_.source.num).max, Bool()))
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@ -60,18 +60,17 @@ object IntImp extends NodeImp[IntSourcePortParameters, IntSinkPortParameters, In
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Vec(ei.size, Vec(ei.map(_.source.num).max, Bool())).flip
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}
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def connect(bo: => Vec[Bool], eo: => IntEdge, bi: => Vec[Bool], ei: => IntEdge)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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def connect(bo: => Vec[Bool], bi: => Vec[Bool], ei: => IntEdge)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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(None, () => {
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require (eo == ei)
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// Cannot use bulk connect, because the widths could differ
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(bo zip bi) foreach { case (o, i) => i := o }
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})
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}
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override def mixO(po: IntSourcePortParameters, node: IntBaseNode): IntSourcePortParameters =
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po.copy(sources = po.sources.map { s => s.copy (nodePath = node +: s.nodePath) })
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override def mixI(pi: IntSinkPortParameters, node: IntBaseNode): IntSinkPortParameters =
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pi.copy(sinks = pi.sinks.map { s => s.copy (nodePath = node +: s.nodePath) })
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override def mixO(pd: IntSourcePortParameters, node: OutwardNode[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]): IntSourcePortParameters =
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pd.copy(sources = pd.sources.map { s => s.copy (nodePath = node +: s.nodePath) })
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override def mixI(pu: IntSinkPortParameters, node: InwardNode[IntSourcePortParameters, IntSinkPortParameters, Vec[Bool]]): IntSinkPortParameters =
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pu.copy(sinks = pu.sinks.map { s => s.copy (nodePath = node +: s.nodePath) })
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}
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case class IntIdentityNode() extends IdentityNode(IntImp)
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@ -6,22 +6,32 @@ import Chisel._
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import scala.collection.mutable.ListBuffer
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import chisel3.internal.sourceinfo.SourceInfo
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// PI = PortInputParameters
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// PO = PortOutputParameters
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// EI = EdgeInput
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// EO = EdgeOutput
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abstract class NodeImp[PO, PI, EO, EI, B <: Data]
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// DI = Downwards flowing Parameters received on the inner side of the node
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// UI = Upwards flowing Parameters generated by the inner side of the node
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// EI = Edge Parameters describing a connection on the inner side of the node
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// BI = Bundle type used when connecting to the inner side of the node
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trait InwardNodeImp[DI, UI, EI, BI <: Data]
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{
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def edgeO(po: PO, pi: PI): EO
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def edgeI(po: PO, pi: PI): EI
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def bundleO(eo: Seq[EO]): Vec[B]
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def bundleI(ei: Seq[EI]): Vec[B]
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def connect(bo: => B, eo: => EO, bi: => B, ei: => EI)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit)
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// If you want to track parameters as they flow through nodes, overload these:
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def mixO(po: PO, node: BaseNode[PO, PI, EO, EI, B]): PO = po
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def mixI(pi: PI, node: BaseNode[PO, PI, EO, EI, B]): PI = pi
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def edgeI(pd: DI, pu: UI): EI
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def bundleI(ei: Seq[EI]): Vec[BI]
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def mixI(pu: UI, node: InwardNode[DI, UI, BI]): UI = pu
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def connect(bo: => BI, bi: => BI, e: => EI)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit)
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}
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// DO = Downwards flowing Parameters generated by the outner side of the node
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// UO = Upwards flowing Parameters received on the outner side of the node
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// EO = Edge Parameters describing a connection on the outer side of the node
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// BO = Bundle type used when connecting to the outer side of the node
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trait OutwardNodeImp[DO, UO, EO, BO <: Data]
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{
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def edgeO(pd: DO, pu: UO): EO
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def bundleO(eo: Seq[EO]): Vec[BO]
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def mixO(pd: DO, node: OutwardNode[DO, UO, BO]): DO = pd
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}
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abstract class NodeImp[D, U, EO, EI, B <: Data]
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extends Object with InwardNodeImp[D, U, EI, B] with OutwardNodeImp[D, U, EO, B]
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abstract class RootNode
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{
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// You cannot create a Node outside a LazyModule!
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@ -39,87 +49,125 @@ abstract class RootNode
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protected[tilelink2] def inputs: Seq[RootNode]
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}
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class BaseNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(
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private val oFn: (Int, Seq[PO]) => Seq[PO],
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private val iFn: (Int, Seq[PI]) => Seq[PI],
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private val numPO: Range.Inclusive,
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private val numPI: Range.Inclusive) extends RootNode
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trait InwardNode[DI, UI, BI <: Data] extends RootNode
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{
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// At least 0 ports must be supported
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require (!numPO.isEmpty, s"No number of outputs would be acceptable to ${name}${lazyModule.line}")
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protected[tilelink2] val numPI: Range.Inclusive
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require (!numPI.isEmpty, s"No number of inputs would be acceptable to ${name}${lazyModule.line}")
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require (numPO.start >= 0, s"${name} accepts a negative number of outputs${lazyModule.line}")
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require (numPI.start >= 0, s"${name} accepts a negative number of inputs${lazyModule.line}")
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val noOs = numPO.size == 1 && numPO.contains(0)
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val noIs = numPI.size == 1 && numPI.contains(0)
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private val accPO = ListBuffer[(Int, BaseNode[PO, PI, EO, EI, B])]()
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private val accPI = ListBuffer[(Int, BaseNode[PO, PI, EO, EI, B])]()
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private var oRealized = false
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private val accPI = ListBuffer[(Int, OutwardNode[DI, UI, BI])]()
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private var iRealized = false
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private def reqO() = require(numPO.contains(accPO.size), s"${name} has ${accPO.size} outputs, expected ${numPO}${lazyModule.line}")
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protected[tilelink2] def iPushed = accPI.size
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protected[tilelink2] def iPush(index: Int, node: OutwardNode[DI, UI, BI])(implicit sourceInfo: SourceInfo) {
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val info = sourceLine(sourceInfo, " at ", "")
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val noIs = numPI.size == 1 && numPI.contains(0)
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require (!noIs, s"${name}${lazyModule.line} was incorrectly connected as a sink" + info)
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require (!iRealized, s"${name}${lazyModule.line} was incorrectly connected as a sink after it's .module was used" + info)
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accPI += ((index, node))
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}
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private def reqI() = require(numPI.contains(accPI.size), s"${name} has ${accPI.size} inputs, expected ${numPI}${lazyModule.line}")
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protected def reqE(o: Int, i: Int) = require(i == o, s"${name} has ${i} inputs and ${o} outputs; they must match${lazyModule.line}")
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protected[tilelink2] lazy val iPorts = { iRealized = true; reqI(); accPI.result() }
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private lazy val oPorts = { oRealized = true; reqO(); accPO.result() }
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private lazy val iPorts = { iRealized = true; reqI(); accPI.result() }
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protected[tilelink2] val iParams: Seq[UI]
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protected[tilelink2] def iConnect: Vec[BI]
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}
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trait OutwardNode[DO, UO, BO <: Data] extends RootNode
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{
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protected[tilelink2] val numPO: Range.Inclusive
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require (!numPO.isEmpty, s"No number of outputs would be acceptable to ${name}${lazyModule.line}")
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require (numPO.start >= 0, s"${name} accepts a negative number of outputs${lazyModule.line}")
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private val accPO = ListBuffer[(Int, InwardNode [DO, UO, BO])]()
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private var oRealized = false
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protected[tilelink2] def oPushed = accPO.size
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protected[tilelink2] def oPush(index: Int, node: InwardNode [DO, UO, BO])(implicit sourceInfo: SourceInfo) {
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val info = sourceLine(sourceInfo, " at ", "")
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val noOs = numPO.size == 1 && numPO.contains(0)
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require (!noOs, s"${name}${lazyModule.line} was incorrectly connected as a source" + info)
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require (!oRealized, s"${name}${lazyModule.line} was incorrectly connected as a source after it's .module was used" + info)
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accPO += ((index, node))
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}
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private def reqO() = require(numPO.contains(accPO.size), s"${name} has ${accPO.size} outputs, expected ${numPO}${lazyModule.line}")
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protected[tilelink2] lazy val oPorts = { oRealized = true; reqO(); accPO.result() }
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protected[tilelink2] val oParams: Seq[DO]
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protected[tilelink2] def oConnect: Vec[BO]
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}
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class MixedNode[DI, UI, EI, BI <: Data, DO, UO, EO, BO <: Data](
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inner: InwardNodeImp [DI, UI, EI, BI],
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outer: OutwardNodeImp[DO, UO, EO, BO])(
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private val dFn: (Int, Seq[DI]) => Seq[DO],
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private val uFn: (Int, Seq[UO]) => Seq[UI],
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protected[tilelink2] val numPO: Range.Inclusive,
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protected[tilelink2] val numPI: Range.Inclusive)
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extends RootNode with InwardNode[DI, UI, BI] with OutwardNode[DO, UO, BO]
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{
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// meta-data for printing the node graph
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protected[tilelink2] def outputs = oPorts.map(_._2)
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protected[tilelink2] def inputs = iPorts.map(_._2)
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private lazy val oParams : Seq[PO] = {
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val o = oFn(oPorts.size, iPorts.map{ case (i, n) => n.oParams(i) })
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private def reqE(o: Int, i: Int) = require(i == o, s"${name} has ${i} inputs and ${o} outputs; they must match${lazyModule.line}")
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protected[tilelink2] lazy val oParams: Seq[DO] = {
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val o = dFn(oPorts.size, iPorts.map { case (i, n) => n.oParams(i) })
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reqE(oPorts.size, o.size)
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o.map(imp.mixO(_, this))
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o.map(outer.mixO(_, this))
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}
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private lazy val iParams : Seq[PI] = {
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val i = iFn(iPorts.size, oPorts.map{ case (o, n) => n.iParams(o) })
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protected[tilelink2] lazy val iParams: Seq[UI] = {
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val i = uFn(iPorts.size, oPorts.map { case (o, n) => n.iParams(o) })
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reqE(i.size, iPorts.size)
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i.map(imp.mixI(_, this))
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i.map(inner.mixI(_, this))
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}
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lazy val edgesOut = (oPorts zip oParams).map { case ((i, n), o) => imp.edgeO(o, n.iParams(i)) }
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lazy val edgesIn = (iPorts zip iParams).map { case ((o, n), i) => imp.edgeI(n.oParams(o), i) }
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lazy val edgesOut = (oPorts zip oParams).map { case ((i, n), o) => outer.edgeO(o, n.iParams(i)) }
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lazy val edgesIn = (iPorts zip iParams).map { case ((o, n), i) => inner.edgeI(n.oParams(o), i) }
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lazy val bundleOut = imp.bundleO(edgesOut)
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lazy val bundleIn = imp.bundleI(edgesIn)
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lazy val bundleOut = outer.bundleO(edgesOut)
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lazy val bundleIn = inner.bundleI(edgesIn)
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def connectOut = bundleOut
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def connectIn = bundleIn
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def oConnect = bundleOut
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def iConnect = bundleIn
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def := (y: BaseNode[PO, PI, EO, EI, B])(implicit sourceInfo: SourceInfo): Option[LazyModule] = {
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// connects the outward part of a node with the inward part of this node
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def := (y: OutwardNode[DI, UI, BI])(implicit sourceInfo: SourceInfo): Option[LazyModule] = {
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val x = this // x := y
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val info = sourceLine(sourceInfo, " at ", "")
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require (!LazyModule.stack.isEmpty, s"${y.name} cannot be connected to ${x.name} outside of LazyModule scope" + info)
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require (!y.noOs, s"${y.name}${y.lazyModule.line} was incorrectly connected as a source" + info)
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require (!y.oRealized, s"${y.name}${y.lazyModule.line} was incorrectly connected as a source after it's .module was used" + info)
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require (!x.noIs, s"${x.name}${x.lazyModule.line} was incorrectly connected as a sink" + info)
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require (!x.iRealized, s"${x.name}${x.lazyModule.line} was incorrectly connected as a sink after it's .module was used" + info)
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val i = x.accPI.size
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val o = y.accPO.size
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y.accPO += ((i, x))
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x.accPI += ((o, y))
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val (out, binding) = imp.connect(y.connectOut(o), y.edgesOut(o), x.connectIn(i), x.edgesIn(i))
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val i = x.iPushed
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val o = y.oPushed
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y.oPush(i, x)
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x.iPush(o, y)
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val (out, binding) = inner.connect(y.oConnect(o), x.iConnect(i), x.edgesIn(i))
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LazyModule.stack.head.bindings = binding :: LazyModule.stack.head.bindings
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out
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}
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}
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class BaseNode[D, U, EO, EI, B <: Data](imp: NodeImp[D, U, EO, EI, B])(
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oFn: (Int, Seq[D]) => Seq[D],
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iFn: (Int, Seq[U]) => Seq[U],
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numPO: Range.Inclusive,
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numPI: Range.Inclusive)
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extends MixedNode[D, U, EI, B, D, U, EO, B](imp, imp)(oFn, iFn, numPO, numPI)
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class IdentityNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])
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extends BaseNode(imp)({case (_, s) => s}, {case (_, s) => s}, 0 to 999, 0 to 999)
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class OutputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp)
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{
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override def connectOut = bundleOut
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override def connectIn = bundleOut
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override def oConnect = bundleOut
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override def iConnect = bundleOut
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}
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class InputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp)
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{
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override def connectOut = bundleIn
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override def connectIn = bundleIn
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override def oConnect = bundleIn
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override def iConnect = bundleIn
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}
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class SourceNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(po: PO, num: Range.Inclusive = 1 to 1)
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@ -146,10 +146,10 @@ object AddressSet
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case class TLManagerParameters(
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address: Seq[AddressSet],
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sinkId: IdRange = IdRange(0, 1),
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regionType: RegionType.T = RegionType.GET_EFFECTS,
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executable: Boolean = false, // processor can execute from this memory
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nodePath: Seq[TLBaseNode] = Seq(),
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sinkId: IdRange = IdRange(0, 1),
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regionType: RegionType.T = RegionType.GET_EFFECTS,
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executable: Boolean = false, // processor can execute from this memory
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nodePath: Seq[RootNode] = Seq(),
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// Supports both Acquire+Release+Finish of these sizes
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supportsAcquire: TransferSizes = TransferSizes.none,
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supportsArithmetic: TransferSizes = TransferSizes.none,
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@ -292,8 +292,8 @@ case class TLManagerPortParameters(
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}
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case class TLClientParameters(
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sourceId: IdRange = IdRange(0,1),
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nodePath: Seq[TLBaseNode] = Seq(),
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sourceId: IdRange = IdRange(0,1),
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nodePath: Seq[RootNode] = Seq(),
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// Supports both Probe+Grant of these sizes
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supportsProbe: TransferSizes = TransferSizes.none,
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supportsArithmetic: TransferSizes = TransferSizes.none,
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@ -8,8 +8,8 @@ import chisel3.internal.sourceinfo.SourceInfo
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object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
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{
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def edgeO(po: TLClientPortParameters, pi: TLManagerPortParameters): TLEdgeOut = new TLEdgeOut(po, pi)
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def edgeI(po: TLClientPortParameters, pi: TLManagerPortParameters): TLEdgeIn = new TLEdgeIn(po, pi)
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def edgeO(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeOut = new TLEdgeOut(pd, pu)
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def edgeI(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeIn = new TLEdgeIn(pd, pu)
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def bundleO(eo: Seq[TLEdgeOut]): Vec[TLBundle] = {
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require (!eo.isEmpty)
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Vec(eo.size, TLBundle(eo.map(_.bundle).reduce(_.union(_))))
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@ -19,19 +19,18 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL
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Vec(ei.size, TLBundle(ei.map(_.bundle).reduce(_.union(_)))).flip
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}
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def connect(bo: => TLBundle, eo: => TLEdgeOut, bi: => TLBundle, ei: => TLEdgeIn)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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val monitor = LazyModule(new TLMonitor(() => new TLBundleSnoop(bo.params), () => eo, sourceInfo))
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def connect(bo: => TLBundle, bi: => TLBundle, ei: => TLEdgeIn)(implicit sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
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val monitor = LazyModule(new TLMonitor(() => new TLBundleSnoop(bo.params), () => ei, sourceInfo))
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(Some(monitor), () => {
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require (eo.asInstanceOf[TLEdgeParameters] == ei.asInstanceOf[TLEdgeParameters])
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bi <> bo
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monitor.module.io.in := TLBundleSnoop(bo)
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})
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}
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override def mixO(po: TLClientPortParameters, node: TLBaseNode): TLClientPortParameters =
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po.copy(clients = po.clients.map { c => c.copy (nodePath = node +: c.nodePath) })
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override def mixI(pi: TLManagerPortParameters, node: TLBaseNode): TLManagerPortParameters =
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pi.copy(managers = pi.managers.map { m => m.copy (nodePath = node +: m.nodePath) })
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override def mixO(pd: TLClientPortParameters, node: OutwardNode[TLClientPortParameters, TLManagerPortParameters, TLBundle]): TLClientPortParameters =
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pd.copy(clients = pd.clients.map { c => c.copy (nodePath = node +: c.nodePath) })
|
||||
override def mixI(pu: TLManagerPortParameters, node: InwardNode[TLClientPortParameters, TLManagerPortParameters, TLBundle]): TLManagerPortParameters =
|
||||
pu.copy(managers = pu.managers.map { m => m.copy (nodePath = node +: m.nodePath) })
|
||||
}
|
||||
|
||||
case class TLIdentityNode() extends IdentityNode(TLImp)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user