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RegMapper: clarify interface is DecoupledIO

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Wesley W. Terpstra 2016-10-02 00:31:14 -07:00 committed by Andrew Waterman
parent 8a268268ad
commit 02f89fb530
1 changed files with 2 additions and 3 deletions
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src/main/scala/uncore/tilelink2/RegMapper.scala
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@ -3,7 +3,6 @@
package uncore.tilelink2
import Chisel._
import chisel3.util.{Irrevocable, IrrevocableIO}
// A bus agnostic register interface to a register-based device
@ -52,8 +51,8 @@ object RegMapper
val inBits = inParams.indexBits
assert (wordmap.keySet.max < (1 << inBits), "Register map does not fit in device")
val out = Wire(Irrevocable(new RegMapperOutput(inParams)))
val front = Wire(Irrevocable(new RegMapperInput(inParams)))
val out = Wire(Decoupled(new RegMapperOutput(inParams)))
val front = Wire(Decoupled(new RegMapperInput(inParams)))
front.bits := in.bits
// Must this device pipeline the control channel?